CVCBLR's VoW blog - Verification on the Web!

In our regular SystemVerilog, VMM trainings ( www.cvcblr.com/trainings ) we demonstrate the power of callbacks to go beyond the obvious usage – specifically a case study to demonstrate transaction level debug. While this topic has been around for very long time (IIRC, Cadence/DAI first provided it via SignalScan), its real application in day-to-day debug has not been as popular as it should probably be. Some reasons for the slow progress in debug are due to the tool limitations, some due to user unawareness etc. Today we had this session again at CVC and users really liked it a lot. We decided to open up this stuff as there is more interest and share it with larger community. We also got Verdi (tm) working on this design with simple addition of $fsdbLog – one doesn’t require extra virtual-interface anymore! Hurray! The Debug champion has once again provided a very useful feature for SystemVerilog, class based environments to be debugged effectively. See some of the screenshots below. A...

As part of our BUDS internship program ( http://www.cvcblr.com/downloads/BUDs_CVC_Acad.pdf ) we work with some of the leading edge educational institutions in India (and one in the USA, BTW). One of our current inters is working on Assertions Based Verification using OVL. In less than a month he has picked up so much so that he says he has learnt more than what he had done (practically) in last semester – it is about that self satisfaction that we consider as our success. During a recent review at his college, his guide, a very respectable professor in this domain (He is the DEAN of M.Tech VLSI there) has given a very constructive criticism saying: OVL is fine, but can you add some research work beyond what is obvious/common use to your thesis? We at CVC felt very happy about that comment – as it reflects on the reviewer’s thirst for highest standards and research inclination and keep us more motivated to go beyond the obvious. So we than him greatly for his inputs via this b...

As in any business, there are always lead players and those who try to “mimic” them. We see our trainings also the same way – let’s admit there are few players in this game in our region. However what sets us apart from the rest? Few: 1. First of all we serve the whole industry at large: Be it a fresh graduate (via our EIC: http://www.cvcblr.com/trng_profiles/CVC_EIC_profile.pdf , http://www.slideshare.net/svenka3/anubhuti-engineering-incubation-centre-eic ) An experienced, mid-career engineer looking to re-skill, recently SystemVerilog being the runaway success ( http://www.cvcblr.com/trng_profiles/CVC_VSV_WK_profile.pdf ) Engineering managers, marketing execs who want 10,000 foot view of the VLSI ball game Sometimes, engineers from other domains (SW, Mechanical – yes we had one!!) willing to learn basics of Verilog. Such a wide coverage of audience is very rare if any, even across globe. Again note that many may promise, it is important to deliver and that too w...

Srinivasan Venkataramanan, CVC Pvt. Ltd. www.cvcblr.com Sreenath V, CVC Pvt. Ltd. www.cvcblr.com One of the many challenges in taking over a block developed by others is the quick ability to grasp the big picture fast and then delve deep into some focus areas. Talking of SystemVerilog based Verification code base (say with a base class such as VMM) is even more challenging as many engineers still find it new. During recent reviews at customer sites we often find engineers asking questions like: 1. How do I quickly know the various transactors in my environment? Of-course one can go through UNIX find-grep route, but with modern verification base, there has to be a modern approach to this ever lasting challenge as well. 2. With several macros being used to reduce the verbosity in coding, the reading/deciphering the code by a novice engineers becomes more challenging. If tools don’t address this part, it is possible that the benefits of code shrink by these macros may get quickl...

  Srinivasan Venkataramanan, CVC Pvt. Ltd. Looks like Jasper DA (www.jasper-da.com) is on a mission to drive simulation a passé J On a more serious note, their recently announced ActiveDesign (TM) technology sounds pretty interesting for early RTL validation. Before I hear that “Aha..that’s my favourite LINTing”, hold on.. this is much more than that – one can see real waveforms– no testbench is ready yet, but the tool can create quality waveforms for you! Sounds too good to be true, well their demo indeed shows a very representative real life design – AHB-lite to AXI bridge with 4 AHB-lite masters. I had a chat with the ActiveDesign team recently to understand what goes “behind-the-scene” (Norris Ip, Holly Stump & Saptarshi all from Jasper). My main doubt on this “early RTL validation” was whether it can work for custom protocols and whether user needs to provide some assertions to get this working. These questions are relevant because we at CVC have prototyped simil...

During a recent look at ActiveDesign product from Jasper ( http://www.jasper-da.com/products/ActiveDesign.htm ), I was pleasantly surprised to see a high quality design being used as the case study. Usually such early product demos contain tightly canned examples, showing only the relevant tool features and much less on the actual design. Here is a refresher – we get a very representative real life design – AHB-lite to AXI bridge with 4 AHB-lite masters, a refreshing change in EDA space. See below for a screenshot of the demo design: Tool demos are not on dummy designs, becoming more and more realistic indeed! On a similar note, Breker’s Trek ( www.brekersystems.com ) has $TREK_HOME/examples that are complete SoC level test synthesis – not just “Hello World”, “foo-bar” anymore! Other interesting designs include a Cache controller model, CPU etc. Similar is the SoC kit initiative from Cadence ( www. cadence .com/products/fv/iv_ kit ) – this one tops the list of all EDA demos ...

During our last week Verification with SystemVerilog class (VSV: http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf ), an interesting question popped up during functional coverage session. As user defined bins are created for vectors in SystemVerilog, what if the value set range is not divisible by the specified number of bins (say in a fixed number of bins case)? Consider: [cpp] bit [4:0] vec_5bits; covergroup cg; cp1 : coverpoint vec_5bits { bins four_buckets [4] = {[0:$]}; bins five_buckets [5] = {[0:$]}; bins fifty_buckets [50] = {[0:$]}; } endgroup : cg [/cpp] Let’s analyze the above: four_buckets –> simple, each contains 8 values, uniform five_buckets –> 5 buckets, first 4 will have 6 values each, 5th bucket will contain all the remaining 8 values: [0,1,2,3,4,5], [6,7,8,9,10,11], [12..17], [18..23], [24,25,26,27,28,29,30,31 ] fifty_bukcets –> first 32 bins will have 1 value each, remaining 18 shall remain empty!! Questa prints a nice warning about th...

Srinivasan Venkataramanan, CVC Pvt. Ltd. Rashmi Talanki, Sasken John Paul Hirudayasamy, Synopsys An extract from a little lengthier post @ http://www.vmmcentral.org/vmartialarts/?p=922 – focus here only on Debug side on this post: One of the powerful features of SystemVerilog is the ability to create TEXT macros (those `define s) with arguments – they can create fairly complex code in jiffy. Take a look at VMM source code if you need examples. In a recent customer engagement, we had to dig deep into VMM atomic Generator code that gets created by the one liner macros! During the coding work, the customer opened up vmm.sv and got trapped in the multitude of `define vmm_atomic_gen_* macros with all those nice looking “ \ “ at the end – thanks to SV’s style of creating macros with arguments. Though powerful, it is not the easiest one to read and decipher – again for a first time SV/VMM user. Now comes the rescue in terms of well proven DVE – the VCS’s robust GUI front end. ...