CVCBLR's VoW blog - Verification on the Web!

  If you live in New Delhi area and are VLSI/EDA/Semicon professional, you won’t like to miss this free event! Come, listen, participate and make difference to how you work tomorrow – by joining standards groups! Date: 10 February 2011, Delhi Signup: https://web.memberclicks.com/mc/quickForm/viewForm.do?orgId=ieee&formId=94222 Location: IIT-Delhi http://www.iitd.ac.in/ Agenda: 8:30 Registration opens 9:00 Welcome— Karen Bartleson (Synopsys) 9:05 IEEE-SA and the World of Standards Dennis Brophy, Member, Board of Governors, IEEE-SA Director of Business Development, Mentor Graphics 9:45 Standards in Design Automation: Influencing Design and Verification Methodologies Low power (1801); Design & Verification productivity (1800, 1735); System Design (1666) Yatin Trivedi, Member, Standards Education Committee, IEEE-SA Director of Standards, Synopsys 10:30 Tea-Break 11:00 Impact of Standards in Design Environment Sri Chandra, Chair, Standards...

Yet another successful Incubation product from CVC, Praveen is now a CAE with Synopsys Hyderabad! Read what he has to say about TeamCVC @ http://in.linkedin.com/in/cvcblr  

  Register before Jan 28th: https://web.memberclicks.com/mc/quickForm/viewForm.do?orgId=ieee&formId=94224   8:30        Registration opens 9:00        Welcome--Pamela Kumar (IBM) 9:05        IEEE-SA and the World of Standards         Dennis Brophy, Member, Board of Governors, IEEE-SA         Director of Business Development, Mentor Graphics 9:45        Standards in Design Automation: Influencing Design and Verification Methodologies         Yatin Trivedi, Member, Standards Education Committee, IEEE-SA         Director of Standards, Synopsys 10:30     Tea-Break 11:00     Impact of Standards in Design Environment ...

Ravi Teja , ASIC Design-Verification Engineer @ www.cvcblr.com &   TeamCVC (Nikhil, Satish, Srini et al.) SystemVerilog is a massive language with several surprises under its belt. Every time you encounter some unexpected result, the first reaction is “Oh! I know System Verilog, this is incorrect behavior of the tool” . Voila! EDA developers get paid *really well* and read the LRM thoroughly before committing their code in. This is not to say that there are no bugs in EDA tools (“bug free EDA tool” is more or less an OXYMORON ). But with System Verilog tools becoming more and more stable and advanced, it is very likely the case that you fall under the famous John Cooley’s signature ( www.deepchip.com ):   So was our recent experience with Aldec’s Riviera-Pro simulator with SystemVerilog constraints.  Let the code speak for itself: class xactn;    rand int var1;    rand int var2;    constraint c_var1 { va...

  They say the best appreciation one can get is through one’s customers’ voice – we at CVC ( www.cvcblr.com ) take every individual trainee as serious as our corporate customers. That has been our reason behind success on both Corporate & individual levels. Here is yet another success story, this time from Md. Kaleem, ASIC Design-Verification Engineer @ Sasken. Kaleem got trained by TeamCVC and also was consulting for us for 2 projects after the training, through which he gained real practical knowledge that has helped him sail through the tough job climate. Kaleem went through our EIC ( http://www.cvcblr.com/trng_profiles/CVC_EIC_profile.pdf ) and then worked on OVM http://www.cvcblr.com/trng_profiles/CVC_DR_OVM_profile.pdf projects before moving on to even better job prospects. Here is what he wrote to us over this weekend! Good luck Kaleem and keep in touch! Mohammed Kaleemulla ( http://in.linkedin.com/pub/mohammed-kaleemulla/23/186/b98 ) Sent: Sunday, January 16, ...

– Satish U, ASIC Design & Verification engineer @ CVC ( www.cvcblr.com ) Every day at work is learning something new. More so when you are asked to work deep into advanced technologies such as SystemVerilog. In a recent project I was asked to delve deep into the constraints portion of SystemVerilog and solve few customer problems in modeling real life traffic pattern generation using SystemVerilog constraints. As part of it, I came up with an interesting to way to visualize the distribution through SystemVerilog covergroup/coverpoint. Though it is little round-about and may not be the best way to “verify” distribution, the technical lead at CVC quickly grasped the value and encouraged to explore more and develop a blog on the same. It is this “cultivating ideas” that makes working at CVC ( www.cvcblr.com ) a perfect blend of learning & fun (and don’t miss it – very aggressive timelines too).              ...