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Big picture – Verification Closure Panel members: Cadence , NextOp , Breker & CVC If you are attending DVCon starting tomorrow, here is a panel that you may not want to skip – yes UVM is hot and ready-to-go. How do we leverage that and get to faster Verification Closure – that’s precisely what we will be discussing in this “Birds-of-a-Feather” panel at DVCon www.dvcon.org on Tuesday Mar 1st, 6.30 PM US/Pacific time at Donner Ballroom , DoubleTree Hotel, San Jose. Here is a summary of what to expect in this panel discussion: UVM is great! Enables interoperable VIPs to be created, reused. In a typical SoC – several such UVM VIPs get integrated and 1 (or more) embedded processors (ARM-like) configure/control the flow. Individual sequences/virtual sequences at UVM level will do great for peripheral-alone testing. Taking right from UVM SoC reference flow @ www.uvmworld.org , here is a sample SOC: How about true “flow/scenario” testing? UVM’s virtual sequencer is “A poss...

  Recently TeamCVC ( http://in.linkedin.com/in/cvcblr ) conducted a 4-day SystemVerilog workshop at Kochi, South India. Some musings at: http://www.cvcblr.com/blog/?p=259   And today we received a cool note from customer voluntarily: Vinayaraj T R, Project Engineer @Cochin: I have attended your training on System Verilog for Verification conducted last week at Kochi.  The session was very much helpful for me and even being a fresher I was able to understand the concepts and gain a lot of knowledge from it. I am very sure that it will help me a lot through out my career. It would be helpful if you could share the lab tutorials of that training. Thank you once again. Regards, Vinayaraj T R, Vinayaraj is certainly not alone. It is this customer satisfaction that gives us the “passion” to do more! Until another customer success story, it is sign-off from Bangalore, TeamCVC

  Are you an expert Verification engineer using upto date languages & methodologies available such as Specman/E, SystemVerilog, VMM, OVM, UVM etc.? Are you looking for even more technologies to find “deeply buried functional bugs” in a language agnostic manner, yet be able to reuse the underlying TB code? Read what Dave Whipp, a veteran HW Verification engineer found working over the last few years: http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=4172   Specifically: There is a pressing need for testing tools that are language-agnostic – and such tools are indeed emerging. The shadow of the SystemVerilog steamroller is lifting. One such tool, that I have been using successfully over the past few years , is Breker’s Trek . Trek randomly generates directed tests using a constrained random walk of a graph (constructed by verification engineers) that describes how an environment interacts with the DUT. This is a step back from the ...

  TeamCVC ( http://in.linkedin.com/in/cvcblr ) is at Cochin, a famous port-city in South India ( http://en.wikipedia.org/wiki/Kochi ) this week on a “Mission SystemVerilog” at a customer site. It is a 4-day program covering: SystemVerilog basics for RTL designers ( http://www.cvcblr.com/trng_profiles/CVC_LG_SVD_profile.pdf )  System Verilog Assertions ( http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf ) SystemVerilog for Verification engineers (VSV: http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf ) The audience is a mix of young, enthusiastic engineers in their early-to-mid career – all very keen to hone their skills on SystemVerilog. Our CTO, Srini ( http://in.linkedin.com/in/svenka3 ) chose to customize the training in a timely manner to get the audience involved and interactive. During Day-2, it was a true “field-day of SystemVerilog Assertions”. Especially when it came to Sequence repetition operators, it was fun all across the roo...