CVCBLR's VoW blog - Verification on the Web!

Last week at DVCon we had a very interesting Birds-of-a-Feather meeting on Mar 1st evening. Panelists included Tom Anderson from Cadence , Yunshan Zhu from NextOp and Adnan Hamid from Breker Systems .   It was moderated by Srinivasan Venkataramanan from CVC . See pre-BoF invite/details at: http://www.cvcblr.com/blog/?p=272 The theme of this panel was “Verification Closure” – given that 2011 DVCon marked the birth/release of UVM standard for developing reusable, inter-operable VIPs, it was a perfect fit for a group of technocrats to explore what is beyond UVM. We had some very interesting discussions and here are some excerpts. If you feel I missed some discussion topic or have any comment on this, feel free to blog it here! To start with, Rick Nordin of Breker Systems introduced the panel topic and the moderator. Srini ( www.linkedin.com/in/svenka3 ) presented single slide setting the stage for the panelists and had the honor of introducing the esteemed panel...

Here are some snaps from recent DVCon UVM poster session. More than 12 vendors demonstrated their commerical offerings around UVM and it was an electrifying experience for the attendees/potential customers (some 180+ UVM tutorial attendees). Products/offerings broadly fell in the following categories: Simulators – Cadence, Synopsys (DOn’t recall Mentor on poster, but of-course Questa supports UVM), another missing poster EDA tool company was Aldec. Though both Mentor & Aldec had their booths at the exhibit. Cadence had a poster on how IUS supports UVM and extended debug features targeted for UVM users. Here is Joesph H with his Cadence poster     Synopsys had a clear, simple poster on how VCS extends its leadership in SystemVerilog performance. Here is Adiel Khan explaining with passion to a customer Synopsys poster:   Register model automation, maintenance: AgniSys dominated the poster with lots of visitors asking questions. Infact their poster a...

At DVCon Accellera released its latest standard for VIP interoperability named UVM – Universal Verification Methodology. 12+ vendors demonstrated their commercial solutions around UVM – hasn’t happened for a long time in the industry around single standard – except perhaps for SystemVerilog itself (back in 2003?) While the technical details can be talked for very long time, here is a practical, real-life experience of “waiting for too long to have this standard”. This could be your simple means of convincing your technical management why they should be looking at UVM seriously in next project. On the DVCon evening (Mar 1st) I was having dinner with a good old friend of mine, Mahesh. Here are his experiences/pains of working with various verification projects for the past 6+ years: Mahesh – it was a nightmare 5-6 years ago for Verification engineers – you move from one project to another within the SAME company (for instance acquired companies in a large company), your way ...