Sledgehammer to crack a nut? – Use right tools for right class of design errors/bugs
I am sure you have heard this phrase before – “A sledgehammer to crack a nut”; the below picture describes it all! Would you use a HUGE hammer to crack a small, tiny nut? (If you are further interested in this phrase read: http://www.phrases.org.uk/meanings/sledgehammer-to-crack-a-nut.html ). I recently had a small design error introduced in a piece of RTL as below: It is an interrupt masking logic, code snippet as below: Note the use of “ANDing” logic – simply, AND- mask with data to produce result .The subtlety in Verilog/System Verilog is that you have 2 seemingly similar operators for doing AND operation; The logical AND: && The bitwise AND: & Given the “loose” data type checking, assignment rules etc. one can get away by using either one of the above many-a-times. In the above case the user used: result = data && mask; With result being a vector the above is a “logical/design error” but usually a Verilog compiler would let this go through (as it is not a...