CVCBLR's VoW blog - Verification on the Web!

In the midst of a cold winter across India, there is some good news for those SystemC enthusiasts. While some in the industry thought the SystemC is being slow in adoption, there has been a constant need for moving up in abstraction in designing electronic systems. Over the past several years several ESL experiments have been carried out by local semiconductor/system companies in India. Incase you are deeply involved in this silent storm, here is your opportunity to broadcast your work as part of The Indian SystemC User’s Group (ISCUG). Abstracts are due by mid-Feb. See details at: www.iscug.in and you may download the CFP (Call For Papers from: http://www.cvcblr.com/downloads/iscug_CallForContribution.pdf See you at ISCUG!

Many users find the factory feature in UVM as quite satisfying and easy to use and believe callbacks are not needed in UVM. However callback is a popular design pattern in software domain (see: http://stackoverflow.com/questions/946834/is-there-a-design-pattern-that-deals-with-callback-mechanism ). It is infact one of the very nice things that came from VMM to UVM. Though it is not that often used in UVM as in VMM, there are some pertinent use cases that makes the callbacks very handy in UVM as well. For instance consider a recent customer requirement that we handled: How to terminate Testcase on Max Error Count Reached? Of-course UVM has this support, but little “hidden” (see http://www.cvcblr.com/blog/?p=203 for similar stuff on VMM). You use the function: set_report_max_quit_count(2); // Quit after 2 errors However in the context of “phasing” this “terminates/interrupts” the phasing rather “abruptly”. While the UVM developers believe this is fine as default behavi...