CVCBLR's VoW blog - Verification on the Web!

Recently Amit (Yet another successful VLSI engineer from CVC’s incubation http://www.cvcblr.com/trng_profiles/CVC_EIC_profile.pdf , asked this: In OVM/UVM ( http://www.cvcblr.com/trng_profiles/Do-it-Right-UVM.pdf ) I am little confused about the way components are hooked-up hierarchically. Consider the code below: In the above constructor ,sometimes I am writing parent =null and some times only parent ,and then passing in super.new();, blindly i am doing this ,but i am not understanding why i am making parent=null and sometime leaving this as parent . what will be the effect of making so. kindly help me. Answer/Explanation: As an enhancement to Verilog, System Verilog allows “default values” for function/task (methods) arguments. By doing so it allows the caller of these methods to have the flexibility in number of arguments – a.k.a variable arguments to a function (though not overloading as in VHDL). So in the example above, the new has 2 arguments, both ha...

A while ago, a user asked : I am trying to check that one of the my inverse clk is reverse of sys_clk: I have written assertions , but when I am seeing this its checking only on falling edge of sys clk ! Please advise property me; @(clk) clk |-> ~clk_inverse; endproperty inverse_pp: assert property (me) else $error ("inverse clk is not inverse as expected", $time);   Here comes the “deferred assertions” to your rescue – a new feature in SVA 2009 LRM. ap_check_inv_clk : assert #0 (clk == !inv_clk); Can be used both inside a procedural block (such as always_comb) or outisde (as a concurrent statement).   Try and let us know if it worked for you – BTW, don’t forget to turn SV 2009 flag ON to your SV tool to compile the above!

As Indian VLSI industry is hiring at crazy rate for verification, SystemVerilog has emerged as a key differentiator in most of the front-end Verification job roles (see: http://www.linkedin.com/groups?homeNewMember=&gid=3706843 ). With many engineers adding SV skills to their CVs – the interviewers are getting tougher and smarter in their questions during interviews. Some related to OOP are below, source: http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=4410 As our CEO posted some code snippet to start with  -we thought we will assist our junior engineers to ponder around the same and explore more on this topic. class base_pkt;   bit b1;   virtual function void display;     $display ("base_pkt: b1: %b", this.b1);   endfunction : display endclass : base_pkt class extended_pkt extends base_pkt;   bit b2;   virtual function void display;   ...

  Here is a recent posting that TeamCVC did on Facebook group ( http://www.facebook.com/groups/199014503449605/ ) , thought it is worth sharing it widely. Bottomline – if you are interested in VLSI, there is nothing that stops you from doing it for free even at college level!   When you say "tools" - a full ASIC platform for free is not realistic, unless it is academic - in which case look at Alliance: http://sourceforge.net/projects/alliancecad/ Though some of the tools in Alliance are industry ready, usually students in India have better tools at their disposal (just that they don't know about it). For instance: Modelsim Student edition http://model.com/content/modelsim-pe-student-edition-hdl-simulation Riviera-Pro student edition: http://www.aldec.com/en/products/university_programs These tools will run on Windows and or Linux. One can install Cygwin ( www.cygwin.com ) and get Linux-like experience on Windows itself (to be ready for industry). Af...