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During one of our recent VSV training sessions, a smart attendee asked few interesting questions about SystemVerilog’s new constructor. Questions like: 1. Is it similar to other functions in Verilog/SV? 2. Is it virtual? 3. What is the return type of the same? 4. How does inheritance work for new ? So here is a blog entry that delves into the “details”. First of all – it is a function – so it can only have non-time consuming stuff (BTW, a task can be invoked via fork..join_none from within a function). It is NOT a virtual function. It is illegal to declare it “virtual”. On the return “type” – it is different from other functions – it is very “adaptive in nature” – i.e. it returns what the LHS requires. i.e. it returns an object of the type of the handle that appears on the LHS. Hence there is NO return type declared for this special function. Things get very interesting/special when a new class is derived from a base class. With any other System Verilog function/task...

With UVM http://www.uvmworld.org/ adding a good framework around SystemVerilog, several ASIC design teams have taken the first step in adopting it in full form. Many are migrating from either OVM or VMM and many others are plain SystemVerilog and/or Verilog users.   One of the significant changes in latest UVM (1.1 onwards) is the so called “phasing” – it is a feature motivated from VMM users and more HW related requirement overlaid on top of more SW centric OVM-like phasing. Refer to a detailed paper on this topic from Intel + CVC @ SNUG India 2011 via: http://bit.ly/JL9x30   A direct impact of this new phasing in UVM 1.1 is that a smooth running test in OVM/plain SystemVerilog is likely terminate “prematurely” in UVM. This is typical when a first time user adds a UVM test as below:   While everything seems normal as in OVM, here is a sample run.log from this test:     The new phasing seems to be in effect : – the reset_phase is kicki...

With so much fever around SystemVerilog in the verification community, more and more junior engineers are picking up System Verilog. Infact several universities started teaching System Verilog as part of advanced VLSI degree. And with its availability in Desktop based simulators like FPGA design tool chain, more and more FPGA designers are looking at it, and adopting it rapidly. Clearly SystemVerilog with its all gun blazing features are useful for FPGA community at large, our CTO Srini presented this at FPGA Camp in Bangalore few years ago: http://www.slideshare.net/mobile/fpgacentral/upgrading-to-system-verilog-for-fpga-designs-srinivasan-venkataramanan-cvc   Since then we have trained several FPGA teams on using: SystemVerilog for Design (SVD: http://www.cvcblr.com/trng_profiles/CVC_LG_SVD_profile.pdf ) SystemVerilog Assertions: (SVA: http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf ) VSV: ( http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf ) ...

  Folks working on AMS (Analog & Mixed Signal) Design-Verification often require real numbers for things like Signal-to-Noise-Ratio (SNR). With so much buzz around SystemVerilog and its clear strengths on Constrained Random Verification support, engineers wonder how they could leverage it for “real randomization”. Unfortunately SystemVerilog doesn’t directly support “rand real” declaration (weird reasons given by EDA developers, while a google on “random float number” reveals quite a few hits). However recall that SystemVerilog is built on top of Verilog and Verilog has some beautiful twin-functions for real <—> bits:   $bitstoreal $realtobits Here is a neat trick to use them for a signal-to-noise ratio random generation (Problem originally reported at: http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=4413 )   Notes: 1. We have used new SystemVerilog 2009 syntax for “extern” constraint – nice one indeed to b...