SystemVerilog foreach loop – an elegant looping option
During this week’s SystemVerilog training, a smart engineer, Sarvendranath created an interesting “derived” example from our regular lab code. After all an engineer is supposed to be “Pedantic” (See an interesting side post on this at: http://www.cvcblr.com/blog/?p=14 ). The topic under discussion was arrays and out-of-bound accesses. This has been talked in detail at various websites for C++ etc. as in: http://w3.ualg.pt/~pjotr/Lectures/PI/WWW/t13.html Consider the below code snippet: The array has 3 unpacked dimensions with bounds at 2,3,4. The “in-bound access” shall be “0..1”, “0..2” and “0..3”. Now what happened during a lab trial was to use an incorrect for loop a shown above with the loop count running from “1..2”, “1..3”, and “1..4” –> The last index has been out-of-bound. Going by several implementation discussions, many tools will not flag this (unfortunately) as it needs to optimize for “performance” and these kind of check...