Catch-up with SVA 2009-2012 updates – free Webinar on Oct 31st
Simplified Assertion Adoption with SystemVerilog 2012 (EU/ASIA) Date: Thursday, October 31st, 2013 Time: 2:00 PM-3:00 PM IST – India time / 9:30 AM-10:30 AM CET (European time) Host: Aldec, CVC’s valued EDA partner ( www.aldec.com ) Presented by: Srinivasan Venkataramanan ( http://www.linkedin.com/in/svenka3 ) CVC (Contemporary Verification Consultants www.cvcblr.com ) – Aldec’s Training Partner, Assertions have been in use for over a decade for now, however, writing detailed, temporal expressions in plain SystemVerilog (SV) 2005 has been at times a demanding task for first time users. While it gets easier as users mature with SVA, the language has made it more straightforward to express complex temporals with recent additions to the standard. With SV 2012 LRM becoming freely available to all use...