CVCBLR's VoW blog - Verification on the Web!

Recently a customer sought a help on how does the UVM’s built-in scoreboard mechanism works, specifically in_order and algorithmic comparators. While he was able to use them well in his design, it when things fail – i.e. he potentially found a design bug he needed additional assistance in debug. By default the UVM framework provides compare() routine for transaction/ uvm_sequence_item . However unlike its predecessor HVLs such as the “E” language (IEEE 1647) or the OpenVera, System Verilog does not have the compare routine built-in to the language itself (for classes). Hence UVM adds it via base class and more. So when we have a transaction model such as: Now by virtue of inheritance, a handy method my_xactn::compare is available.  So one can use it to compare 2 objects of this type as shown below:   Note: in the above code snippet the return value of compare is unused, in actual code of-course you should assert it/throw an `uvm_error etc. Now, when we simulate this wit...

Recently an ABV early stage user/explorer realized it is little hard to get started with OVL-VHDL-Modelsim combination. It surprised us as  it would many others in the industry, having known how well folks at Mentor have been supporting OVL, VHDL etc. As valuable QVP partner with Mentor, we at TeamCVC decided to make it easier for end users. When we dug further we did realize it is not out-of-the-box. Hence we created a quick start example and uploaded it to our website. Feel free to grab it from here: http://www.cvcblr.com/downloads/ovl_vhdl.tgz   It is certainly a quick example just to demo the flow. Will add more soon. Here is the README for the example: CVC's OVL VHDL Example with Modelsim -------------------------------------- To compile and run OVL VHDL example in Questa/MTI follow this example We've used ovl_one_hot on a DUMMY signal, just to demo the flow. You need latest OVL 2.7 release. We've included a part of that in this tar ball To run ---...

Victor Lyuboslavsky, Victor EDA, technology partner, guest blogger at CVC Ever wondered if you can run Verilog Sims from a Web Browser? Well , playing with Verilog and OVL has gotten a little easier recently thanks to the introduction of EDA Playground . EDA Playground is a web application that allows users to edit, simulate, share, and view waves for their HDL code. It is intended to accelerate the learning of design and testbench development with easier code sharing and with simpler access to simulators and libraries. EDA Playground is free , and, since it is web-browser based, it runs on any OS . And you can be up and running in few minutes, without having to install EDA tools, licenses etc. EDA Playground has two editor panes. The left one is intended for testbench code, and the right one intended for design code. The bottom pane is for simulation results, which are updated in real time when the simulation is running. Running a simulation is easy -- select the simulator on the o...

For those VHDL folks exploring advanced verification techniques such as ABV (Assertion Based Verification), here is some trick for you all! A many of you would be aware VHDL 2008 standard incorporated IEEE 1850 PSL (VHDL flavor) in it and much before that EDA tools supported PSL + VHDL as a good combination. One of the earliest tutorials on PSL and most widely read one is available @ http://www.project-veripage.com/psl_tutorial_1.php and was authored by our CEO Mrs. Ajeetha Kumari. As it can be seen in the tutorial PSL makes ABV adoption really simple and effective and leads to immediate benefits to the design verification cycle. One of the not-so-uncommon requirements from user community of VJDL + PSL is the ability to refer to PSL events/status from within VHDL Testbench code. This could then be used for PASS/AIL detection, coverage etc. A nice trick in PSL is to use “endpoints”.  Now coming to specific syntax, there are2 variants – in Accellera version of PSL, endpoint was a...

During our recent SystemVerilog Assertions update webinar ( http://www.cvcblr.com/blog/?p=802 ) one of the audience raised a question on how to check asynchronous events using SVA. Here comes a quick response with code. Also simulated using Aldec’s Riviera-PRO tool.   As you can see in the picture, no clock involved per-se, but use the start and end events themselves as clock for the SVA. So, if you’ve more challenging requirements, do drop in at CVC and we will assist you resolve them! TeamCVC BuzzNet Tags: Verilog , SystemVerilog , SVA , ABV , Aldec , EDA