CVCBLR's VoW blog - Verification on the Web!

As we get to the end of an eventful 2013 and look forward to a great 2014, TeamCVC is at Manipal, a beautiful coastal town in the West coast of India. Surrounded by Arabian sea coast on one side and Western Ghats on the other, this is the ideal place for a peaceful research center and it is no co-incidence that the famous Manipal University is housed here. Coming to this town and conducting a 10-day boot-camp on SystemVerilog and UVM has been a pleasure so far as we have a young, talented, enthusiastic set of attendees. One thing that we continuously get asked during our VSV training sessions is – which SystemVerilog LRM to refer to? While the Google search reveals several PDFs, it gets quite confusing to a newcomer which one to pickup and refer to. In the past it used to be the due to “lack of reliable, legal reference” as the IEEE LRM was available at a cost. However the IEEE 1800-2012 LRM got released for free of cost, thanks to the IEEE GIT program. So go ahead and get a legal, ...

  Static design verification through thorough RTL analysis started several years ago, with early stage ones simply being “linters” and the later, advanced ones combining some of formal techniques as well. One of the most common complaints by RTL teams while using linters is the SNR – Signal-2-Noise Ratio of the endless set of errors/warnings from the tool. So much so that we have heard of customers giving up on linters, primarily those freebies/bundled with simulator ones. While it is true that some of the reported ones are indeed serious issues, the ROI (Return On Investment) of having RTL designers navigating through the ocean of messages is too little in many cases. OTOH there are clear set of issues that a good LINTer can spot for you quite easily, for instance see: Sledgehammer to crack a nut? – Use right tools for right class of design errors/bugs : http://www.cvcblr.com/blog/?p=377   Essentially it comes to the art of “Finding the needles in the haystack” and in...

In one of our recently concluded UVM training sessions at CVC a customer asked how easy is it to migrate an existing proven code base running with VMM to UVM. Since this is a very common situation, we at CVC have put together a detailed set of case studies and a half-a-day workshop on this topic. As a starting point we ask few simple questions to the customer on their code base so that we can provide an estimated effort involved in the migration. Invariably we start asking “Which VMM version do you run?” – and many are actually unaware :-( Here is a tiny piece of code that would get the answer right from your simulation: A small VMM-built-in utility class is provided as part of VMM named vmm_version . It has few interesting methods, First one being:     The first one displays the major-minor versions such as 1.11 and vendor name. Typically EDA vendors customize these opensource libraries to add debug features and at times to fix incompatibilities across implementations. ...

To all the ASIC Verification enthusiasts interested in pushing the limits beyond existing languages and methodologies, here is your chance to contribute and be part of the change. As many would be aware, IEEE 1647 standard defines Functional Verification language e . For over a decade e language has provided many advanced features for verification engineers that have recently been adopted to other languages such as SystemVerilog as well. The most recent one being “soft constraints” – see: http://www.cvcblr.com/blog/?p=629   And as more customers demand more features, the working group on e language has been busy adding new proposals. In our last group meeting we agreed on having four working sub-groups. http://www.eda.org/twiki/bin/view.cgi/P1647/Meeting78Minutes These are:- 1)      Temporal Working Group 2)      Messaging Working Group 3)      Types and Operators Working Group 4)    ...