Low Power Verification with UPF made easy - attend this free training
CVC, world leader in VLSI training is glad to bring a free session on Low Power Verification with UPF. Come and join us for a free, half-day event to learn about UPF (Unified Power Format) IEEE 1801 standard. We will start from basics, present key low power concepts and then move onto how using Static tools such as Cadence CLP (Conformal Low Power) and Mentor Graphics' Questa can find low power related bugs. Schedule: Session 1 - Aug 24th, 2019, Saturday 11AM to 1 PM -Register via: https://tinyurl.com/upfclp Session 2 - Aug 28th, 2019, Wednesday 11AM to 1 PM