CVCBLR's VoW blog - Verification on the Web!

Recently we were asked a good & interesting question: How do I use "soft constraint" in the macro `uvm_do_with? What would be the syntax? I say this is a good & interesting b'cos of 2 things: 1. The SV LRM doesn't give an explicit example for this (it is fine, not that it should, LRM is not a textbook) 2. The use case should be considered (This specific user had a good need - for automatic coverage closure - or ACC). Now quickly jumping to solution, based on our SystemVerilog 2012 tutorial that our CEO Ajeetha delivered at IIT Mumbai earlier in 2014 ( http://on.fb.me/1yfcBSx ), here is a code snippet: For those who need a quick background on what are soft constraints , see: http://www.cvcblr.com/blog/?p=629   Now with 3 major EDA vendors supporting this syntax, you should leverage on this more!

Recently one of CVC’s successful alumni, Harshal posted a nice challenge for SystemVerilog newcomers. Harshal has gone through our time trusted, long term SystemVerilog course and got placed at Synopsys and his career has been growing ever since. The original post describing the background is at: http://goo.gl/oq4FmF Crux of it was to “reverse the ordering” or change endianness of a bit stream. While a really rudimentary approach would be to do bit-by-bit as in:   bit [7:0] msb_vec, lsb_vec; msb_vec[7] = lsb_vec[0]; msb_vec[6] = lsb_vec[1]; // … While the above works, it is hard to maintain, upgrade for larger sizes etc. He attempted to automate it using Verilog (V2K)’s bit-slicing as in:   msb_vec [(28-i)] = lsb_vec[(0+(i))-:1]; //Bit Slicing logic But hold on, there is even a smarter way in SystemVerilog, use the “bit streaming” operator: $display (" msb_vec: %b reverse: %b", msb_vec, { << {msb_vec} } ); If the array was unppacked, there is a built-in array.reverse() ...

At DVCon-14, leading EDA vendor MENT has taken the initiative to propose a Test Specification Standard (see: http://www.goo.gl/BKuNEd ). Given that SV & UVM are well established and deep into their development, stability and adoption phase, the innovation has to come at next level of abstraction. Over the last decade, we at CVC have been working with customers (semiconductor design houses) and EDA partners in defining, evangelizing and deploying multitude of technologies and languages such as OVL, e/Specman, eRM, PSL, SVA, SV, VMM, OVM, AVM, UVM etc. While most of them address the key aspects of "how verification shall be effectively carried out", the next level of "What defines my verification space" has been left for adjacent technologies. Now with this new initiative we are starting to see this problem being addressed. Here is a quick summary of various attempts that have been made to address this problem so far. Hopefully the new Accellera committee will loo...

As we get to the end of an eventful 2013 and look forward to a great 2014, TeamCVC is at Manipal, a beautiful coastal town in the West coast of India. Surrounded by Arabian sea coast on one side and Western Ghats on the other, this is the ideal place for a peaceful research center and it is no co-incidence that the famous Manipal University is housed here. Coming to this town and conducting a 10-day boot-camp on SystemVerilog and UVM has been a pleasure so far as we have a young, talented, enthusiastic set of attendees. One thing that we continuously get asked during our VSV training sessions is – which SystemVerilog LRM to refer to? While the Google search reveals several PDFs, it gets quite confusing to a newcomer which one to pickup and refer to. In the past it used to be the due to “lack of reliable, legal reference” as the IEEE LRM was available at a cost. However the IEEE 1800-2012 LRM got released for free of cost, thanks to the IEEE GIT program. So go ahead and get a legal, ...

  Static design verification through thorough RTL analysis started several years ago, with early stage ones simply being “linters” and the later, advanced ones combining some of formal techniques as well. One of the most common complaints by RTL teams while using linters is the SNR – Signal-2-Noise Ratio of the endless set of errors/warnings from the tool. So much so that we have heard of customers giving up on linters, primarily those freebies/bundled with simulator ones. While it is true that some of the reported ones are indeed serious issues, the ROI (Return On Investment) of having RTL designers navigating through the ocean of messages is too little in many cases. OTOH there are clear set of issues that a good LINTer can spot for you quite easily, for instance see: Sledgehammer to crack a nut? – Use right tools for right class of design errors/bugs : http://www.cvcblr.com/blog/?p=377   Essentially it comes to the art of “Finding the needles in the haystack” and in...

In one of our recently concluded UVM training sessions at CVC a customer asked how easy is it to migrate an existing proven code base running with VMM to UVM. Since this is a very common situation, we at CVC have put together a detailed set of case studies and a half-a-day workshop on this topic. As a starting point we ask few simple questions to the customer on their code base so that we can provide an estimated effort involved in the migration. Invariably we start asking “Which VMM version do you run?” – and many are actually unaware :-( Here is a tiny piece of code that would get the answer right from your simulation: A small VMM-built-in utility class is provided as part of VMM named vmm_version . It has few interesting methods, First one being:     The first one displays the major-minor versions such as 1.11 and vendor name. Typically EDA vendors customize these opensource libraries to add debug features and at times to fix incompatibilities across implementations. ...