SystemVerilog Soft constraints usage in `uvm_do_with macro

Recently we were asked a good & interesting question:

  • How do I use "soft constraint" in the macro `uvm_do_with? What would be the syntax?

I say this is a good & interesting b'cos of 2 things:

1. The SV LRM doesn't give an explicit example for this (it is fine, not that it should, LRM is not a textbook)

2. The use case should be considered (This specific user had a good need - for automatic coverage closure - or ACC).

Now quickly jumping to solution, based on our SystemVerilog 2012 tutorial that our CEO Ajeetha delivered at IIT Mumbai earlier in 2014 (http://on.fb.me/1yfcBSx), here is a code snippet:

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For those who need a quick background on what are soft constraints, see: http://www.cvcblr.com/blog/?p=629 

Now with 3 major EDA vendors supporting this syntax, you should leverage on this more!

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