CVCBLR's VoW blog - Verification on the Web!

16 Aug 2009: http://www.livemint.com/2009/08/16131752/Corporate-India-resumes-hiring.html?h=A1 This is a very refreshing read indeed and inline with CVC’s prediction on the market. It is very important not to jump too many steps too fast and call it honky-dory, it is essential that we stay on the floor, do the basics and get the ecosystem back on track. For fresh graduates this is an ideal opportunity to acquire right skills needed in the industry and not fall prey to “name-sake” trainings. Start with “END” in mind – ask the right set of questions; ensure you have confidence in the team that you would work with during a training/incubation to see that your career is being built and not just a set of language skills.   For recently displaced workers – this is better than ever time to hone their skills to grab the opportunities as they open up locally, slowly. Do not rely just on openings at job-portals. For the past 6 months we at CVC have been assisting various VLSI compan...

1-day course on “Do-it Right – Advanced VMM” …SystemVerilog framework for creating effective Verification Environment CVC (www.cvcblr.com) is announcing a new session of its 1-day course on “Do-it Right – Advanced VMM” including new base classes and RAL . Duration Topic Duration Advanced VMM 1 day The course is structured in a balanced manner with theory and lab sessions tightly embedded in a manner that helps in mastering topics learned so far in the course. Schedule: August 19 th at Bangalore To attend this class, confirm your registration by sending an email to training @ cvcblr.com Ph: +91-9916176014, +91-80-42134156 Please include the following details in your email: Name: Company Name: Contact Email ID: Contact Number:

2-days course on “Do-it Right – Basic VMM” …SystemVerilog framework for creating effective Verification Environment CVC (www.cvcblr.com) is announcing a new session of its 2-days course on “Do-it Right – Basic VMM” - a step-by-step guide to building scalable, reusable and flexible Verification Environment using VMM. Duration Topic Duration Quick SystemVerilog refresh 0.5 day Verification Methodology 1.5 days The course is structured in a balanced manner with theory and lab sessions tightly embedded in a manner that helps in mastering topics learned so far in the course. Schedule: August 12 th ,13 th at Bangalore To attend this class, confirm your registration by sending an email to training @ cvcblr.com Ph: +91-9916176014, +91-80-42134156 Please include the following details in your email...