CVCBLR's VoW blog - Verification on the Web!

Those die-hard fans of VHDL (and maybe even those from Verilog camp), see: Tarun’s Facebook page: http://www.facebook.com/profile.php?id=100001085815092   He says: Was VHDL created specifically to harass people? Though we support both HDLs, clearly Verilog/SystemVerilog is emerging as most favorite. But in case you need to use VHDL, remember to pick up Emacs mode with VHDL – you will be easily 40% faster! See http://www.iis.ee.ethz.ch/~zimmi/emacs/vhdl-mode.html

If you haven’t registered yet, goto: http://user2user.mentor.com/bangalore-india-2010.html   With Wally Rhines speaking, you can’t afford to miss his power-packed keyonte. Also this year there is Mr. John Colley of www.deepchip.com presenting a session. Known for his open, user-focused comments on various tools, technologies & vendors (sometimes creating controversies too) this is one session that’s worth beating Bangalore traffic to be there! BTW, John is also looking for good survey questions focused on Indian audience and issues concerning Indian users of Mentor tools. So do send them across via www.deepchip.com   See you there at Mentor’s U2U on Dec 10th. Look for TeamCVC ( www.cvcblr.com ) in the crowd and we can chat! TeamCVC, www.cvcblr.com/blog

Quick summary of what I liked at recent CDNLive India. Read live tweets @ www.twitter.com/cvcblr First of all, the venue is FRESH – ITC Royal Gardenia hotel, a welcome change from regular Leela/Taj :-) Second, the first few sessions were JAM-packed with more than 25 customers standing (with all seats occupied). This was surprising as the audience beta the Bangalore traffic to be there at around 9.30 AM. On the technical front, well let’s focus on what we know best – Front-end Design & Verification. Frankly – I was not alone who got totally confused about which “Verification” track to choose from. There was this “FED + Verification track” System Design & Verification track I first though it was the FED that I should be in, as it contained one of my much awaited Nokia paper on Formal/ABV/IFV usage. But my good friend @CDN Maruthi Srinivas helped with clarification. His explanation: First of all sorry for confusion, this year we had so many good papers on Ver...

IP reuse, RTL/Design IP-reuse to be precise has been in effect for over a decade now, thanks to the time-tested RMM book, http://amzn.to/bI04yK and the extensive support of those rules/guidelines/policies by Lint tools such as SpyGlass, ALINT (from www.aldec.com ), and recently Ascent (from www.realintent.com ). However while talking to a customer recently on their Printer SoC verification challenges, some interesting facts/stats emerged: Yes we reuse IPs, they are Si-proven, but… New SoCs use these IPs in very different context leading to: Different configurations that were never used/tested/verified before Order of configuring these IPs can make-or-break the systems The “ordering” was more interesting and in recently concluded CDNLive India, Deeapk from Freescale Noida presented an excellent paper on: “ Corner Case Verification with IFV and assertions” . While much has been blogged about the recently concluded event CDNLive, this paper didn’t get enough mention ...

As recent EDAC panel discussed the impact of Social Media in VLSI/EDA marketing (see: http://bit.ly/dzd3Ev ) it is quite clear that one alone can’t make a difference, no matter how loud you shout – it is the collective ecosystem – of company-customers-partners that can make a win-win case in this new age marketing. Refer to Altera’s slide on that from http://bit.ly/dzd3Ev Jim @ Altera says that it is the customer-to-customer interaction happening via Social Media that makes the bigger impact. Given the post-recession ramp-up at many semiconductor houses, teams are very selective in investing/exploring/adopting new technologies and they are all looking for true success stories and real user views than just tool/feature updates. Now looking at Karen @Synopsys’s views: it is the GEEK-2-Geek connection that she/Synopsys is bullish about to leverage on this new media. While she quotes SNUG group @ linkedin.com, we found even more interesting stats with Verification specific gro...

It is becoming more and more popular to find users writing SVA for VHDL too – though the VHDL-2008 has PSL inside it and most of the EDA tools (Aldec, Cadence, Mentor & Synopsys) have good support for PSL-VHDL. Recently a customer asked: "The SVA binding port mismatch error only when I bind an VHDL output port to a SVA input port. But, when i bind a Verilog output port to a SVA input port, it compiles without a problem ".   While it does look like a tool-specific issue, in old VHDL, an output port can’t be read, need a buffer type for the same. When you bind a SVA to a VHDL output port, SVA tries to “read” it. It is a subtle issue – though many tools have relaxed this “semantic” check on VHDL side. Also VHDL-2008 allows reading of output ports IIRC. Check with your EDA vendor if you see this issue, they ought to be supporting it already! Cheers TeamCVC www.cvcblr.com

Whichever methodology you use for Verification (if you don’t use, better start with UVM maybe) – some of the tasks & requirements are common. One of them is the ability to control certain simulation features across runs without needing to recompile. Classicial examples are: Dumping different scopes Changing Verbosity (for debug, regression runs etc.) Choosing tests Stopping after N-number of errors It is the last one that one of our customers recently had an issue with, here is an extract from his email: I need clarification regarding " vmm_log:stop_after_n_error ".  Want to know whether there is command line equivalent of the same. I do not want to edit any of the source file but rather control from the command line.  Does the language/methodology has in built construct for the same ? Interestingly an OVM user also asked for it during our recent OVM training ( www.cvcblr.com/trainings ) at their site. In OVM it is “max_...