SystemVerilog Assertions for VHDL

It is becoming more and more popular to find users writing SVA for VHDL too – though the VHDL-2008 has PSL inside it and most of the EDA tools (Aldec, Cadence, Mentor & Synopsys) have good support for PSL-VHDL.

Recently a customer asked:

"The SVA binding port mismatch error only when I bind an VHDL output port to a SVA input port. But, when i bind a Verilog output port to a SVA input port, it compiles without a problem ".

  While it does look like a tool-specific issue, in old VHDL, an output port can’t be read, need a buffer type for the same. When you bind a SVA to a VHDL output port, SVA tries to “read” it.

It is a subtle issue – though many tools have relaxed this “semantic” check on VHDL side. Also VHDL-2008 allows reading of output ports IIRC. Check with your EDA vendor if you see this issue, they ought to be supporting it already!

Cheers

TeamCVC

www.cvcblr.com

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