CVCBLR's VoW blog - Verification on the Web!

Samurai is a hard hitting warrior with never-say-die attitude. So far as Debug is concerned, the verification engineers become Samurai especially when it comes to Gate Level Debug with timing violations. Here is a breather for those non-Samurai s class of engineers coming to you from an advanced Debug integration in Mentor’s Questa debug platform ! If you have been through GLS (Gate Level Simulation) – you are sure of this topic; If you are a honest individual you would admit it is one of the most dreaded debug issues that you see in your DV life! When those timing violations appear here is what w do: Go over the library files to locate the $setp/$hold specifications, Occasional LRM reading to recall the arguments to those system tasks Decipher the specparam value (recall it could be a complex expression involving other specparam, parameters, `define – and last but not the least, any SDF overrides via LABEL) Now once you have this so called “static” information, t...

They say “ innovation never stops ” – it is true for the SystemVerilog language committee. And it is very true for our co-author Ben Cohen, who even at the retired age keeps updating himself on latest on SV, VMM, OVM, UVM and of-course SVA. Ben Cohen is the Accellera nominated representative for the SV-AC committee on IEEE dev team. See TOC at: http://systemverilog.us/SVA3rdE_preface_toc.pdf The cover of this book is a NASA photograph of Mars, taken by Curiosity. Just like how Mars is enormously big, the verification state space of most of the modern day designs are extremely large. While there have been several advances in the area of "stimulus" or "activation of potential design errors", the amount of checking being done during such activation (either via simulation or formal analysis) demands detailed, precise design specification. This is precisely where SVA fits in the design flow. Just like how the whole world awaits pictures & findings from Curiosity ...