Are you a Debug Samurai? Debugging Timing violations – the dreaded $setup/$hold

Samurai is a hard hitting warrior with never-say-die attitude. So far as Debug is concerned, the verification engineers become Samurai especially when it comes to Gate Level Debug with timing violations. Here is a breather for those non-Samurais class of engineers coming to you from an advanced Debug integration in Mentor’s Questa debug platform!

If you have been through GLS (Gate Level Simulation) – you are sure of this topic; If you are a honest individual you would admit it is one of the most dreaded debug issues that you see in your DV life! When those timing violations appear here is what w do:

1. Go over the library files to locate the $setp/$hold specifications,
2. Occasional LRM reading to recall the arguments to those system tasks
3. Decipher the specparam value (recall it could be a complex expression involving other specparam, parameters, `define – and last but not the least, any SDF overrides via LABEL)
4. Now once you have this so called “static” information, the real fun starts – find the time at which clock changed, then the data changed, do the math and reason out why the violation is

By the time you get to the step-4 above you are exhausted (usually, unless you are a verification/Debug Samurai ).

Now it is not all that bad – especially if you are a young engineer willing to invest time and energy, at CVC’s EIC course (http://www.cvcblr.com/trainings teach this in detail. Here are 2 slides from our CFV course (http://www.cvcblr.com/trng_profiles/CVC_IN_CFV_profile.pdf):

 

And the next one:

 

During our deep-dive Verilog training today for a bunch of IIT graduates, this topic of “timing checks” came up and the young, new army (with potentially few Samurai class engineers too, hopefully) wanted to understand this in detail. Creating an example is easy part, debugging the failures and making sense of it in real project is the tougher part. Here is where Mentor’s Questa debug platform comes very handy. For many years, the messages from $setup/$hold checks are considered the BEST in Verilog (across simulators, to be fair). But what makes Questa more intuitive and easy to use is their “message viewing” automated internally and annotated in Waveform at the top; below is a series of screenshots with little text to explain!

Enjoy reading and even more – enjoy debugging. No more “dreaded debug of $setup/$hold” – hopefully!

First the DFF with timing checks:

 

And here comes the waveform for a few setup/hold violations:

 

The plain vanilla log/transcript is below:

To be fair – the above is a great debug message provided by Verilog (and every tool does print the above, I suppose). It does tell you what time the clock and data changed and the setup/hold parameter value. So what’s the big deal in Questa? It is the “message integration” to the waveform Sir!

Here is the debug flow:

• Double-click on the message in console window
• It takes you the Waveform
• Places the cursor on exactly the TIME at which this  error occurred (with reasonable zooming around)
• At the top of Wave, you have the SAME message annotated (see below):

The annotated messages can be “navigated” just like any other signal value changes! Now with few girds added, you can quickly see that:

• At 113 ns “d” changed
• At 115 ns “posedge clk” occurred
• SETUP time is “3 ns” – Voila! – there is that violation!

Similarly for the HOLD violation:

 

So if you are lucky – your debugger would do this integration and save you hours!

Met Vriendelijke Groeten (As the Dutch & German say):

TeamCVC

www.cvcblr.com/blog