OTG – On-The-Go SystemVerilog tip: Assoc arrays – allocate OTG

Sparse arrays in general (in many computer languages) exhibit ‘allocate-on-the-go” behavior. System Verilog is no exception. During today’s VSV training at CVC we had some interesting discussion on this topic. SV assoc-arrays get allocated on-the-go, while it is well known and talked about fact – it is clear for the “write” to array. What about “read”? For some early stage users it is not so obvious that a $display is a reader as well. Consider the following piece of code (full code later):

logic [7:0] logic_aa [int];

initial

  logic_aa[20] = 121;onthego

In the above code the 21st location gets allocated OTG, clear.

What about the following?

logic [7:0] logic_aa [int];

initial

  $display (“%m CVC: read AA: “, logic_aa[20] );

What would you expect? Error? Or allocate OTG? Hold your answer, let’s see full code:

aa_1 onthego

Any guess? Well, the $display on an un-allocated assoc-array element is a reader too, hence gets allocated OTG (On-The-Go), default value gets assigned. Isn’t that somewhat “not so good”? Well, that’s why a good tool like Questa (from Mentor) emits a warning in such case, see below:

aa_2

So next time when you use assoc-array ensure you recall this OTG behavior!

Safe journey with SV and CVC :-)

TeamCVC 

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