Comprehensive Functional Verification (CFV)

Title: Comprehensive Functional Verification (CFV)
Location: www.cvcblr.com
Link out: Click here
Description: See contents, agenda at: http://www.cvcblr.com/trng_profiles/CVC_IN_CFV_profile.pdf

Mainly for new comers, FPGA designers
Start Date: 2009-12-4
End Date: 2009-12-8

Comments

Post a Comment

Popular posts from this blog

Smart one-liner for bit inversion in SystemVerilog

Recently one of CVC’s successful alumni, Harshal posted a nice challenge for SystemVerilog newcomers. Harshal has gone through our time trusted, long term SystemVerilog course and got placed at Synopsys and his career has been growing ever since. The original post describing the background is at: http://goo.gl/oq4FmF Crux of it was to “reverse the ordering” or change endianness of a bit stream. While a really rudimentary approach would be to do bit-by-bit as in:   bit [7:0] msb_vec, lsb_vec; msb_vec[7] = lsb_vec[0]; msb_vec[6] = lsb_vec[1]; // … While the above works, it is hard to maintain, upgrade for larger sizes etc. He attempted to automate it using Verilog (V2K)’s bit-slicing as in:   msb_vec [(28-i)] = lsb_vec[(0+(i))-:1]; //Bit Slicing logic But hold on, there is even a smarter way in SystemVerilog, use the “bit streaming” operator: $display (" msb_vec: %b reverse: %b", msb_vec, { << {msb_vec} } ); If the array was unppacked, there is a built-in array.reverse() ...
Read more

VHDL + PSL action blocks – quick guide

Image
For those VHDL folks exploring advanced verification techniques such as ABV (Assertion Based Verification), here is some trick for you all! A many of you would be aware VHDL 2008 standard incorporated IEEE 1850 PSL (VHDL flavor) in it and much before that EDA tools supported PSL + VHDL as a good combination. One of the earliest tutorials on PSL and most widely read one is available @ http://www.project-veripage.com/psl_tutorial_1.php and was authored by our CEO Mrs. Ajeetha Kumari. As it can be seen in the tutorial PSL makes ABV adoption really simple and effective and leads to immediate benefits to the design verification cycle. One of the not-so-uncommon requirements from user community of VJDL + PSL is the ability to refer to PSL events/status from within VHDL Testbench code. This could then be used for PASS/AIL detection, coverage etc. A nice trick in PSL is to use “endpoints”.  Now coming to specific syntax, there are2 variants – in Accellera version of PSL, endpoint was a...
Read more

Low Power Verification with UPF made easy - attend this free training

CVC, world leader in VLSI training is glad to bring a free session on Low Power Verification with UPF. Come and join us for a free, half-day event to learn about UPF (Unified Power Format) IEEE 1801 standard. We will start from basics, present key low power concepts and then move onto how using Static tools such as Cadence CLP (Conformal Low Power) and Mentor Graphics' Questa can find low power related bugs. Schedule: Session 1 - Aug 24th,  2019, Saturday 11AM to 1 PM -Register via:  https://tinyurl.com/upfclp  Session 2 - Aug 28th, 2019, Wednesday 11AM to 1 PM
Read more