SystemVerilog User Group (SVUG) Bangalore - Twitter updates

 

Here is a copy-paste of my Twitter updates on recent SVUG Bangalore event. Yes I know it is (was) a bad posting style on newsgroup to do “top-posting” but with new era Twitter-like information sharing, is it that bad? Aren’t people getting used to that style?

 

Catch me on Twitter @ http://www.twitter.com/sricvc

  1. Explaining complex topic such as OVM in 1 hour is hard, more so in post lunch session..12:45 AM Nov 11th from mobile web

  2. a persistent issue Ive with young AEs - too many usage of superlative language12:32 AM Nov 11th from mobile web

  3. Ashish on OVM intro.. doing a good job12:25 AM Nov 11th from mobile web

  4. the doc from accellera has high level "redirection" session, good stuff..12:03 AM Nov 11th from mobile web

  5. Dennis on VIP interoperability standard12:02 AM Nov 11th from mobile web

  6. Great 2 sessions, most useful for designers12:01 AM Nov 11th from mobile web

  7. cliff has been very pedantic and pragmatic in his presentations12:00 AM Nov 11th from mobile web

  8. can i add sva to class - another blog? use virtual intf10:53 PM Nov 10th from mobile web

  9. if vs. immediate sva;; good Q - watch for next blog at cvcblr.com/blog for better answer10:52 PM Nov 10th from mobile web

  10. good Q - how to add sva on 2 signals coming from 2 separate modules with bind?10:50 PM Nov 10th from mobile web

  11. Dennis told me that majority of attendees are verif folks, are they excited with such detailed character savings??10:30 PM Nov 10th from mobile web

  12. for 13 sva, from 79 lines to 40 to 27..10:27 PM Nov 10th from mobile web

  13. excellent illustration on line count reduction via macros10:26 PM Nov 10th from mobile web

  14. Cliff really likes longggg.. labels, good guidline, how many will stick to??10:25 PM Nov 10th from mobile web

  15. worth mentioning sv09 checker..10:22 PM Nov 10th from mobile web

  16. mentions sv09 few times.. default arg for macros..10:21 PM Nov 10th from mobile web

  17. makes a nice reco on using macros for designers to reduce sva verbosity10:20 PM Nov 10th from mobile web

  18. he continues with same dff sva... arrghhh10:18 PM Nov 10th from mobile web

  19. multi line macros right in V95, did you know that??10:18 PM Nov 10th from mobile web

  20. designers hate verbosity of property, assert etc..10:16 PM Nov 10th from mobile web

  21. practical tip - watch number of parenthesis in assertions..10:15 PM Nov 10th from mobile web

  22. for sva class I can never do without a laser pointer, to point to the attempt/thread10:14 PM Nov 10th from mobile web

  23. shows a DFF assertion - ok for ppt , never do that in real life10:11 PM Nov 10th from mobile web

  24. shows immediate assert use with randomize(), from a methodology view it is better to add warn/err and provide handle to user to stop or not10:10 PM Nov 10th from mobile web

  25. cliff on sva tips for designers10:07 PM Nov 10th from mobile web

  26. motivation for rtl designers to add sva - less interrupt from silly TB mistakes, valid interrupts are fine though..10:06 PM Nov 10th from mobile web

  27. sva circle of life.. interesting10:00 PM Nov 10th from mobile web

  28. Is final blk in SV disallow $strobe? worth checking..9:33 PM Nov 10th from mobile web

  29. Kishore on $display and $strobe.. good Q9:33 PM Nov 10th from mobile web

  30. At SVUG Bangalore today, full house9:32 PM Nov 10th from mobile web

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