Enabling Faster ABV – new initiatives

Assertion Based Verification has certainly been one of the mostly debated topics over the last half-a-decade. So much so that one of the past DVCons was full of SystemVerilog & PSL papers on ABV that someone commented it is “ABV conference” than DVCon (was it DVCon 2005?2006?)

Even then the adoption rate has been slower than expected – agreed by many stats, EDA folks etc. A relatively new EDA vendor is addressing it via some tools, see: http://www.zocalo-tech.com/index.php 

Not clear how easy it will be and how much ROI users will see, but an interesting development I must say.

With SystemVerilog 2009 LRM adding checker constructs we predict that the adoption of OVL-like libraries should dramatically improve. We explained it thoroughly in our SVA handbook 2nd edition, see: http://www.cvcblr.com/blog__resources 

We have a DVCon 2010 paper on this very topic, see: http://dvcon.org/events/eventdetails.aspx?id=108-3 

Let’s see how fast the checker gets implemented by EDA tools, we used VCS for our new book http://www.systemverilog.us/sva_info.html

Hope 2010 brings ABV more and more into RTL engineer’s desktops!

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