Magma releases/enhances SystemVerilog Synthesis tool

Read:

http://www.benzinga.com/pressreleases/g50108/magma-announces-talus-design-1-1-and-talus-rtl-1-1-enhanced-synthesis-products-

While SV-Design for Synthesis has been talked for a while now, except for some big design houses, we are yet to see full time adaptors. My own experience with SV-Interface synthesis has been bad to say the least – with all extra identifier lengthy names we end up with. Also my suspicion is lack of Formal Verification, Lint and other tool support that makes it even more difficult for Design community. For instance in the above PR, Magma says:

Today, most SoC designers use formal verification tools to confirm the final design is equivalent to the source RTL. The process of determining whether identified errors are actual problems often lengthens the design cycle. Talus Design 1.1 and Talus RTL 1.1 include output scripts that simplify and accelerate verification for users of Cadence's industry-leading equivalence checker, Conformal(R).

What’s not very clear to me is the level of SystemVerilog Design support in formal tools. I personally know of many Model checking vendors with close to 0 support for SV-Design!

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