VHDL 1076-2008 – process (all)

As we close on our Advanced VHDL training, some users were wondering if there is an equivalent of SystemVerilog’s always_comb in VHDL. The issue is not about comparing one language with another, rather how to ease the pain of keeping the sensitivity list of a process upto date with design changes. VHDL 2008 allows “all” as sensitivity list in a process.

So instead of writing:

[cpp]
LOG : process(CLK, RESET, SIG1, SIG2, SIG3, SIG4)
[/cpp]

One can now do:

[cpp] LOG : process( all)
[/cpp]

So happy VHDL coding! On tool support – Anand from my team just now told me Aldec’s Active-HDL supports it. I’m sure there are more tools supporting it too!

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