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… Tuesday Technote on Solver Debug, Jijo PS, Srini TeamCVC www.cvcblr.com Dealing with simple solver failure – looking for really “quick help”. It is a layered SystemVerilog code for a SAN Router. An inherited constraint in a testcase showed randomize() failure. Before you jump to conclusion on the simple nature of the problem – consider that this is the first time ever I look at this design/env as the original author moved out of the company (sign of good times :-) ?) and am given to fix the code ASAP – in next 15 minutes that’s (sounds way too familiar, Huh?). # Number of fware xactn 19 # ** Fatal: [Time 0 ns] Test cfg Solver failure #    Time: 0 ns  Scope: san_rt_top.san_rt_test_pgm_0.b1.lp.a1 File: ../ rt_test_03.sv Line: 83 # ** Note: Data structure takes 9699728 bytes of memory #          Process time 0.03 seconds #          $finish    : ../test/san_rt_test_03.sv(83) #    Time: 0 ns  Iteration: 2  Instance: /san_rt_top/san_rt_test_pgm_0 So what next? Consult our friendly Questa S...

…Reflections from core engineering team of CVC - fresh from SNUG India 2010 Jijo PS, Thirumalai Prabhu, Kumar Shivam, Avit Kori, Praveen & Nikhil – TeamCVC www.cvcblr.com 2010 has been a great year so far for us the verification community in India – with constant news of fresh hirings, new project starts etc. For us at CVC things have been as busy as we would like them to be – both from trainings and consulting perspective. Now that we have an army of VMM-aware engineers, we decided to let them see how the different product companies leverage on the matured methodology during SNUG India 2010, earlier this week. The results were amazing – every one of the attendees thanked us for letting them feel the vibrant VMM straight from the horse’s mouth – the real users, developers etc. Here is a quick collection of various VMM updates from SNUG India 2010 – as seen by TeamCVC. Expect to hear more on VMM1.2 soon from us as now I have a young team all charged up with VMM 1.2 (thanks to Amit @...

Recently Dr. M M Pallam Raju, Honorable Minister of State for Defense, Government of India, released ISA-Frost & Sullivan 2009-11 India Semiconductor Market Update. Here are excerpts from his speech during this release:   To face tomorrow, the Indian semiconductor industry has to rise to meet the challenges from other Asian countries and aid in developing the ecosystem. China and Vietnam are emerging as strong competitors in this industry. The Indian industry will have to address certain vital links in its ecosystem, such as systems engineering, venture capital and IP protection, to become more robust. It will also have to take measures to build up a skilled and technically trained, design-aware workforce for the future.   CVC is well poised to address this very challenge – both in terms of creating the workforce and delivering top-notch services to the industry. Look at our EIC: http://www.slideshare.net/svenka3/anubhuti-engineering-incubation...

If you have all been waiting for the UVM booth @ DAC, here is more to cheer about – a new “UVM reference flow/kit” is being donated (Apache/Limited GPL license) to the UVM community. For a change, we now have “true reference verification kit” that’s openly available to download, try it on any SystemVerilog simulator of your choice. For sure TeamCVC ( www.cvcblr.com ) is giving it a try on all 4 (or even the 5th one – Verdi) very soon. More details at: http://www.uvmworld.org/blog/?p=115

Srinivasan Venkataraman, Chief Technology Officer, CVC Pvt Ltd ( www.cvcblr.com ) TeamSpecman representatives for this Blog interview: Kishore Karnane, Adam Sherer, Hannes Froehlich, and Ariel Melchior During recent ClubT India session I met the famous “TeamSpecman ( www.twitter.com/teamspecman )” to see what’s new about Specman/ e and general verification roadmap from them. To my pleasant surprise they offered much more than what I got to know from regular e WG updates (CVC is part of the e WG @ www.ieee1647.org to contribute & stay on top of the upcoming language updates therein). The Incisive team has joined hands with the Specman team to roll out the “Specman Advanced Option” for power users of verification. Now, just around DAC time, I got a chance to interview the “TeamSpecman” including some of their core R&D folks to delve a little deep into the motivation behind the updates, some of them being rolled out and others in pipeline. What resulted is the following int...

Given the business climate and local commitments, it is hard for me to be at DAC. But with keen focus on Verification it is kind of important for CVC ( www.cvcblr.com ) to share our thoughts on fresh ideas/technologies on Verification that are being demo-ed at DAC-2010 ( www.dac.com ). Leaving the BIG-3 out (I hope to blog about them prior to DAC on what we see as “updates” from them separately), here is a quick round-up of what we see as promising solutions that any DAC attendee in Verification domain might be interested. Feel free to comment via our blog @ www.cvcblr.com/blog – we would love to hear them! NextOP One of the most promising start-ups in the assertion based verification domain. They have been in stealth mode for a few years. Only recently quite a bit of information has been let out about their technology. It all started with an eval report from a real user and active follow-ups from then – see: http://www.cvcblr.com/blog/?p=147 Ben Cohen ( www.systemverilog.us ) recentl...