Vibrant VMM becomes even better at SNUG India 2010

…Reflections from core engineering team of CVC - fresh from SNUG India 2010

Jijo PS, Thirumalai Prabhu, Kumar Shivam, Avit Kori, Praveen & Nikhil – TeamCVC www.cvcblr.com

2010 has been a great year so far for us the verification community in India – with constant news of fresh hirings, new project starts etc. For us at CVC things have been as busy as we would like them to be – both from trainings and consulting perspective. Now that we have an army of VMM-aware engineers, we decided to let them see how the different product companies leverage on the matured methodology during SNUG India 2010, earlier this week. The results were amazing – every one of the attendees thanked us for letting them feel the vibrant VMM straight from the horse’s mouth – the real users, developers etc. Here is a quick collection of various VMM updates from SNUG India 2010 – as seen by TeamCVC. Expect to hear more on VMM1.2 soon from us as now I have a young team all charged up with VMM 1.2 (thanks to Amit @SNPS).

WRED Verification with VMM

In her paper on “WRED verification with VMM”, Puja shared her usage of advanced VMM capabilities for a challenging verification task. Specifically she touched upon:

· VMM Multi-Stream Scenario gen

· VMM Datastream Scoreboard with its powerful “with_loss” predictor engine

· VMM RAL to access direct & indirect RAMs & registers

What we really liked is to see real application of some of these advanced VMM features – we were taught all of these during our regular CVC trainings and we even tried many of them on our own designs. It feels great to hear form peers on similar usage and to appreciate the value we derive out of VMM @CVC and the vibrant ecosystem that CVC creates around the same.

As they say, a well stated problem is half-a-solution. In this case the presenter did a great start by correlating Bangalore’s erratic traffic pattern to that of a “congested network”. Alas VMM can’t really solve road traffic woes, maybe just yet, anyone want to give it a try?

System-Level verification with VMM

Ashok Chandran, of Analog Devices presented their use of specialized VMM components in a system-level verification project. As a junior engineer, I often wondered where exactly will we seek the help of specialized VMM base classes like vmm_broadcast and vmm_scheduler

At the end the audience learnt what are some of the unique challenges a SoC verification project can present. Even more interesting was the fact that the ever growing VMM seems to have solution for a wide variety of such problems, well thought-out upfront – Kudos to the VMM developers!

Ashok also briefed on his team’s usage of relatively new features in VMM such as vmm_record and vmm_playback and how it helps us to quickly replay streams. At times VMM seems to have too many features, especially for juniors, but it is this kind of exposure that we get during SNUG that opens up our eyes to a wider world of reality!

On the tool side, a significant learning for me (Jijo) was the usage of separate compile option in VCS, am sure to add in my future work.

VMM 1.2 for VMM users

Amit from SNPS gave a very useful and upto-the-point update on VMM 1.2 for long time VMM users. When we learnt VMM at CVC and started developing VMM-envs, we always felt more automation is feasible. Infact we had an intern project on writing scripts for the same (such as the start_xactor for instance). It was rejuvenating to listen to the VMM 1.2 run_tests feature and the implicit phasing techniques. Though look like little “magic” these features are bound to improve our productivity as there are lesser things to code-debug and move-on..

Amit also touched upon the use of TLM 2.0 ports and how they can be nicely used for integrating functional coverage, instead of using the vmm_callbacks. With due credits to the power of callbacks – as a junior I always longed for a simpler means to integrate functional coverage – and here comes my savior J

The hierarchical component creation and configurations in VMM 1.2 puts us on track for the emerging UVM and is very pleasing to see how the industry keeps moving to more-n-more automation and makes us realize that Verification is a HOT topic and is bound to be so for years to come. Glad to be Verification Engineer J

A truly vibrant ecosystem enabled by CVC -VMM Catalyst member

A significant addition to this year’s SNUG India was the DCE – Designer Community Expo – a genuine initiative by Synopsys to bring in partners to serve the larger customer base better all under one roof. CVC (www.cvcblr.com) being the most active VMM catalyst member in this region was invited to setup a booth showcasing its offerings. As noted in another blog on CVC (www.cvcblr.com/blog) it was a near stampede response in our booth as we gave away several books including our popular VMM adoption book http://systemverilog.us/?p=14 and all the new SVA Handbook 2nd edition http://systemverilog.us/?p=16 .

Here is a snapshot of CVC’s booth with our VMM and other offerings.

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