UVM gets better with a complete Reference Flow

If you have all been waiting for the UVM booth @ DAC, here is more to cheer about – a new “UVM reference flow/kit” is being donated (Apache/Limited GPL license) to the UVM community. For a change, we now have “true reference verification kit” that’s openly available to download, try it on any SystemVerilog simulator of your choice. For sure TeamCVC (www.cvcblr.com) is giving it a try on all 4 (or even the 5th one – Verdi) very soon.

More details at: http://www.uvmworld.org/blog/?p=115

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