CVCBLR's VoW blog - Verification on the Web!

With the overwhelming marketing buzz around the modern day verification languages such as SystemVerilog and methodologies such as VMM, OVM, UVM etc. I at times feel sorry for those real soldiers of the Verification army – who carry out most of the verification execution as they are left behind a lot untouched by these “happening stuff”. For them all it matters is “Now that I have a failure, how soon can I narrow down” the same? In an earlier article in TeamCVC blog, we explored the amount of debug that goes on in the industry, see: http://www.cvcblr.com/blog/?p=93   Yet, the amount of investment that goes into debug automation is not as much as it should really be – partly the users are to blame – they do NOT often speak out LOUD asking for those “right” features with their vendors. For a change, this time at SNUG India 2011 some of the audience questions were specifically targeted at this exact Debug menace. Few samples for those who missed it out: During Gate Level s...

Last week at SNUG India , LSI presented a good paper on the topic of Functional Coverage reuse (See: http://www.synopsys.com/Community/SNUG/India/Pages/Abstracts.aspx?loc=India&locy=2011#TA1 ) Challenges and Approaches for Functional Coverage in SOC Verification Environments Manikandan Subramanian, Ron Jacob, Sasidhar Dudyala, Srishan Thirumalai [LSI] This paper describes the complexity in using block level functional coverage at top level and pitfalls and approaches to aid reuse. This also describes controllability on coverage infrastructure from block level to SOC level and how UVM-EA helped in building the layered testbench infrastructure that can be reused. What I really liked about this is the level of maturity that the SystemVerilog adoption that this paper indicates in India – while functional coverage is one of the top few powerful features in System Verilog, its adoption has been traditionally slower than what we wished. Especially with the boatload of fe...

If you’ve missed being at SNUG India DCE 2011 – you’ve truly missed out the high spirits of a great ambience, great food and even greater freebies flowing in from all the participating companies – ranging from bags, pens, mugs, Android Phones, quick reference guides (SVA, UVM), Apple iPods, iTouch, and believe-it-or-not – the all new iPhone4 and of-course the best of all, the popular and most useful SystemVerilog books in the earth: SystemVerilog Assertions, 2nd edition (with IEEE 1800-2009 updates), Pragmatic Approach to VMM adoption and the PSL, IEEE 1850, now part of VHDL- 1076-2009 . TeamCVC’s booth was naturally focused on our core strength, some of the most popular Advanced Verification trainings in India and soon more globally too: Given the vibrant ecosystem with 22+ participating companies setting up their booths, the ambience was amazing, electrifying and something that Leela Palace “GRAND Ballroom” was literally struggling to cope-up with. There were more than ...

Earlier this week at SNUG India 2011 , Intel had a very interesting and pragmatic paper on just “how rudimentary” the code coverage analysis tools are as of today. The presenter Ishwar did a great job in all aspects – right from having chosen the right number of slides, clarity and keen focus on the problem he chose to talk about. Let’s start with the basics – below is a trivial Toggle cov report from VCS’s URG (just as a sample, every major simulator has similar viewer)   While the color coding, hierarchical reporting etc. are useful – the “uncovered” hole analysis is where the users spend lot of time analyzing just “what is not covered and why”? Ishwar’s team has done some out-of-the-box thinking and shown how a simple, logical way to approach the analysis can bring quick results than the “raw” approach that many might follow – blame it on the tools not giving better assistance, if you will. He used 3 criteria to prioritize which holes to look at: How “close” is the n...

On June 17th 2011 IEEE RevCom has approved the latest updated version of IEEE-1647 e-standard. Some of the exciting new additions include: Named constraints – a la SystemVerilog constraint blocks, helps in debug, review etc. Much awaited “real” data type – we asked for it back in 2004! Wish granted some 7 years later, better late than never! It also indicates that the language is very much alive and kicking! Type constraints Constraint extensions – with is only e templates – much like C++ – better than user written complex macros Named checks – more useful for tools to do “failure triage” for instance A full fledged “Reflective API” a la Verilog’s VPI As noted in recent Cadence blog entry: http://www.cadence.com/Community/blogs/fv/archive/2011/06/16/is-e-old-yes-is-it-outdated-definitely-not.aspx?CMP=home   e is old but NOT dead! It is alive and kicking!   Now it is almost time to start contributing to next-gen E language, if you want to ...

If you live in India, specifically Bangalore and work in the field of VLSI, it is hard to miss the well attended SNUG event every year. Just like last year, this year’s SNUG hosts the popular DCE - Designer Community Expo   http://www.synopsys.com/Community/SNUG/India/Pages/DCE.aspx   TeamCVC ( www.cvcblr.com ) will be at Verification track booth and you are welcome to stop by for a range of surprises, quiz & gifts including our various books ( www.systemverilog.us ). TeamCVC also has a paper co-authored by our CTO Srini ( www.linkedin.com/in/svenka3 ) along with Kishor @Intel and Amit @SNPS, see abstract at: http://www.synopsys.com/Community/SNUG/India/Pages/Abstracts.aspx?loc=India&locy=2011#TA1   What: OVM/UVM paper with Intel-CVC-SNPS: http://www.synopsys.com/Community/SNUG/India/Pages/Abstracts.aspx?loc=India&locy=2011#TA1 When: Thursday June 23, 2011, 10.30 AM Where: Leela Palace Hotel What: Meet TeamCVC @ our booth, DCE: Win books, ...

At DAC 2011, Cadence introduced yet-another 3-letter buzzword to the wonderful world of Verification – ADS: Assertion-Driven Simulation . Traditionally assertions have been monitors/passive elements, but some high-end formal verification groups have been using it to drive model checkers, random stimulus generators etc. CVC ( www.cvcblr.com ) has a long history with assertions and we saw this ADS model first with a start-up named Safelogic in Sweden, that got acquired by Jasper a while ago. Under the hood most of the formal tools could do this – be it CDN’s IFV, SNPS’s Magellan etc. Jasper rolled out ActiveDesign in 2010 and TeamCVC spoke to the developers and blogged it at http://www.cvcblr.com/blog/?p=132 Recently Zocalo ( www.zocalo-tech.com ) announced VisualSVA product that enables capturing of SVA via a GUI and also provide debug traces And now Cadence brings it even more closer – down to your Simvision window – with a push of an additional button in your favorite Waveform w...