Need for more Debug automation – atlast the real user spoke about it @ SNUG India
With the overwhelming marketing buzz around the modern day verification languages such as SystemVerilog and methodologies such as VMM, OVM, UVM etc. I at times feel sorry for those real soldiers of the Verification army – who carry out most of the verification execution as they are left behind a lot untouched by these “happening stuff”. For them all it matters is “Now that I have a failure, how soon can I narrow down” the same?
In an earlier article inTeamCVC blog, we explored the amount of debug that goes on in the industry, see: http://www.cvcblr.com/blog/?p=93
Yet, the amount of investment that goes into debug automation is not as much as it should really be – partly the users are to blame – they do NOT often speak out LOUD asking for those “right” features with their vendors.
For a change, this time at SNUG India 2011 some of the audience questions were specifically targeted at this exact Debug menace. Few samples for those who missed it out:
- During Gate Level simulations I see failures say timing violations. How do I correlate the log/console to VPD and the source code – it is pretty much manual and takes way too much time.
- The answer lies with some of the advanced capabilities being developed as you could see in: http://www.vmmcentral.org/vmartialarts/category/debug/
- Many modern day waveform viewers provide a nice automation to link these automatically, ask you vendor for more
Amit Sharma did a commendable job in running like the recently introduced Duronto Express of Indian Railways: http://en.wikipedia.org/wiki/Duronto_Express in covering a whole of VCS/DVE/VIP updates in his tutorial. Many wondered if the audience were able to cope up, but surprisingly there were so many involved audience queries that proved such speculations wrong by miles!
Another interesting Debug related query was to do with the Protocol Analyzer feature that Amit introduced and its applicability to custom interfaces. Interestingly the same has been discussed as recently as last week in Accellera’s UVM extensions to add more callbacks to the UVM 1.1 to allow extended transaction recording. If you want to contribute to the same, join us at: http://www.accellera.org/activities/vip
It will be interesting to see what the debug focused EDA companies like SpringSoft, and the new EDA kid Vennsa have to offer in this space.
Comments
Post a Comment