Pinning down SystemVerilog program block

One of the verification related constructs in the vast SystemVerilog language is the program construct. It is also one of the most debated features as to whether it is needed or not. Sure it is very well supported by all EDA tools, and heavily promoted by Synopsys with their VMM to start with. OVM (from Mentor & Cadence) didn’t advocate it though and in fact they discourage it. With UVM – it is a 50-50 – if you like it, use it, else don’t bother.

From a technical perspective we at CVC like the fact that we now have a clear TB-2-DUT separation. We do teach this during our regular VSV training sessions (http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf).

Here comes a 2-minute run-down on this nice feature. Let’s look at some code:

 

PGM_1

Line 6: #10 DUT ‘reads” a signal named “sig_1”.

Line 14: #10 TB “drives” the same signal “sig_1” (They are connected, not shown above)

Consider that the above “write” and “read” to the signal were done on “module” scope – this is potential “race” – as 2 different simulators can schedule these 2 initial blocks in arbitrary order. Such a race will be painful to debug, hard to migrate, harder to maintain etc. So how does bringing in program help here? Assuming you are familiar with System Verilog event scheduling mechanism (we cover this in detail during our SVA training - http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf) one would recall that there is a region named “REACTIVE” region that executes AFTER the “design” region/assignments. The program block code executes in this reactive region thereby avoiding the races by language! One could visualize this by running the code above in any SV tool. Here is a snapshot with Mentor’s Questa 10.2:

PGM_2

 

As you can see in the log/transcript, the “DUT” gets done first and then comes the TB/program block – all in same time-stamp though.

Now that being guaranteed to be consistent across EDA tools, users have one-less thing to worry about in their Verification journey.

Do send your comments via training@cvcblr.com

Regards

TeamCVC

Comments

Popular posts from this blog

Smart one-liner for bit inversion in SystemVerilog

SystemVerilog Soft constraints usage in `uvm_do_with macro

Easier PLI integration with MPSim