UVM-ML is here: Funcntional Verification is heterogeneous in nature - notes from DAC 2013

As part of my recent DAC 2013 minutes, here are some of the musings from customer experiences around DAC this year (and some from projects we have been doing in 2012-13 here).


While there is a large set of customers exploring SystemVerilog in its full capacity and with UVM, make no mistake - not many will throw away what has been done previously and that was precisely my talking point at DAC 2013 theater presentation earlier this June.


Below are some of the slides I presented to get you started:



And it is in this context the recently announced UVM-ML initiative from Accellera http://www.accellera.org/apps/org/workgroup/mlwg/ becomes very relevant to every verification team. It is still very much open and all of you can contribute to developing this to be useful to the verification community at large. You can learn more about this UVM-ML from this Cadence blog:  http://bit.ly/14IdjrA


See you soon at UVM-ML conference calls/discussions.


TeamCVC



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