CVCBLR's VoW blog - Verification on the Web!

As you all may know by now, IEEE 1800-2009 was recently approved. There were many updates in SystemVerilog core, the Assertions , and the addition of the checker , a new type of entity where several assertions and verification code can be defined just like a module/interface. In addition the checker can be inlined procedurally unlike a module. Immediate next step will be to get real users exposed to the power of new constructs. We would expect tool vendors to start adopting this new version, probably sooner than we may think as some vendors were actively implementing the new features as the LRM was being refined. Now atleast 2 major EDA vendors have released support for varying sets of constructs from this new LRM. Ping your EDA support for updates! As far as book support, we're please to announce the release of our SystemVerilog Assertions Handbook, 2nd Edition that includes the IEEE 1800-2009 updates. For more information, see http://systemverilog.us/sva2_toc_prefa...

  December is usually the time of holidays, relatively work load etc. Given the challenging job scenario this is also the best time to hone your skills and face the New Year with new skills, explore new job avenues, segments etc. CVC is announcing a week long certificate course on standard protocol verification. At the end of this course you would have finished developing a MIP (Monitor IP) for a standard protocol based on SVA. Assertions are very powerful to capture temporal behavior. Broadly it covers the following topics: ABV Introduction SystemVerilog Assertions (SVA) Project – develop a real life Protocol Monitor IP (MIP) with SVA Course contents:  http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf Topic Duration SystemVerilog Assertions 2.0 days Project ...

  December is usually the time of holidays, relatively work load etc. Given the challenging job scenario this is also the best time to hone your skills and face the New Year with new skills, explore new job avenues, segments etc. CVC is launching its highly successful 2 weeks certificate course on Functional Verification using SystemVerilog with a project in one of the following domains. · Networking · Communication · Image Processing VFest also focuses the language aspect SV in depth. Broadly it covers the following topics: SystemVerilog basics (SVB) http://www.cvcblr.com/trng_profiles/CVC_LG_SVD_profile.pdf Verification Using SystemVerilog (VSV) http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf Verification Methodology (VM) Duration Topic Duration SystemVerilog Basics 0.5 day Verification using SystemVer...

  …Step upto ASIC world with SystemVerilog, Assertions & Testbench CVC (www. Technorati Tags: trainings cvcblr.com) is announcing a new session of its 10-day course on “FPGA-2-ASIC_DV-with SystemVerilog” - a step-by-step approach to introduce modern day Design & Verification challenges & solutions for FPGA designers. It is structured as follows: Basic Session Comprehensive Functional Verification (CFV) SystemVerilog basics (SVB) Advanced Session ABV Introduction SystemVerilog Assertions (SVA) Project – develop a real life Protocol IP (PIP) with SVA Verification Using SystemVerilog (VSV) Course contents:  http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf Topic Duration Comprehensive Functional Verific...

Title: CFV + SystemVerilog basics Location: www.cvcblr.com Link out: Click here Description: SystemVerilog basics. Look at SVB portion from this profile: http://www.cvcblr.com/trng_profiles/CVC_VSV_WK_profile.pdf This is intended mainly for FPGA designers, so the focus will be building fundamentals than building complex OOP testbench. Start Date: 2009-12-8 End Date: 2009-12-9

Title: Verification Using SystemVerilog (VSV) Location: www.cvcblr.com Link out: Click here Description: Our popular corporate training on SystemVerilog for Verification. Details at: http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf Start Date: 2009-12-5 End Date: 2009-12-7

Title: Comprehensive Functional Verification (CFV) Location: www.cvcblr.com Link out: Click here Description: See contents, agenda at: http://www.cvcblr.com/trng_profiles/CVC_IN_CFV_profile.pdf Mainly for new comers, FPGA designers Start Date: 2009-12-4 End Date: 2009-12-8

Title: Advanced VHDL for Verification Location: www.cvcblr.com Link out: Click here Description: Advanced VHDL techniques for Functional Verification. For a close-door customer, not a public class. Start Date: 2009-12-2 End Date: 2009-12-3

Title: Verilog HDL Location: www.cvcblr.com Link out: Click here Description: Basic Verilog HDL Start Date: 2009-11-25 End Date: 2009-11-26

Recently an interesting question was raised by SystemVerilog user on randc usage with enum . To illustrate, consider the following code: [cpp] typedef enum {red, green, blue, yellow, white} house_color_type; class c; randc house_color_type enum_0; [/cpp] Spot anything wrong above? Perhaps not? As it goes with randc an implementation needs to remember all values generated so far before recycling! So it does consume extra memory. SV LRM says: To reduce memory requirements, implementations may impose a limit on the maximum size of a randc variable, but it shall be no less than 8 bits. By default an enum is an int – i.e. 32-bits, hence allowing a randc on it blindly is a real challenge for tools – though some advanced tools/versions (Questa 6.5a for instance) allows it. But this default int choice is not something I like so much – it should have been cleverer to choose appropriate sized of vector by the implementation, did we not know LRM committee is often biased by implementers. No p...

Folks, here is my “trip report” or “Tweet report” from recent CDNLive 2009, Bangalore. I really wish to spend more time in fixing typos, arranging it, consolidating it, summarizing etc. but man it is already 00.49 hours here and I have 2 more hours of OVM debug left for a paying customer, so here you go the “live” tweets from CDNLive!   Drop me a note if you have comments, would love to hear them. And if anyone felt offended by this post (especially some of the presenters being criticised, no pun intended, just straight forward, live feedback – that’s it!   Ish has been a power user of formal, hybrid and is grilling... 1:28 AM Nov 19th from mobile web Ish Dham from TI is a judge, good pick CDN 1:27 AM Nov 19th from mobile web another good ! - how to qualify formal env? again not a good answer, sorry folks... 1:24 AM Nov 19th from mobile web not a very convinci...

A rare event in the EDA industry – a company standing up and offering full-featured tool for free INCLUDING for *commercial* usage and not for weeks, but 6 FULL MONTHS ! Here is VeriloggerExtreme – a full fledged V2K simulator (GUI + batch mode, with powerful debugger) for free! Company claims it is 10X faster than the typical FPGA targeted low end simulators. Let’s see how it performs. Read more @: http://www.syncad.com/pr_verilogger_extreme_free_2009.htm   See: http://www.syncad.com/verilogger_verilog_simulator.htm   On our day-1 with it, we found that the doc isn’t clear that much on how to use it. (The Help didn’t come up due to lack of some *.sh file), but then do $TOOL_HOME/bin, see vlogcmd , try it and it WORKS, voila!   Watch this space for more updates!

Posted On behalf of Ajeetha Kumari & P.Ramya, CVC Pvt Ltd,          Here is a small eval report of SynaptiCAD’s Transaction Tracker back conducted a while back. We will relook at it in next couple of weeks as part of internship (see: http://www.cvcblr.com/downloads/BUDs_CVC_Acad.pdf ). We looked at Transaction Tracker as a GUI front-end to adopt ABV (using PSL/SVA). This means that the users have identified a set of specification/requirements in a natural language such as English, but they are not specialists in an assertions language such as PSL. This tool will let them capture the requirements as PSL assertions without them having to learn the language to start with. This tool shall also be quite handy in assertion classes being run by non-EDA vendors such as my company (CVC www.noveldv.com ). The tool itself is stable, I don't remember it crashing, so a good sign :-) Its error messaging needs lot of improvement especially if it were to ...

Interesting blog from Pradeep @ http://pradeepchakraborty.wordpress.com/2009/11/18/what-does-it-take-for-students-to-be-semiconductor-industry-ready/   A topic that’s kind of vibrant for the past several years (if not forever). What I really like about these observations is the “ Do look for apprenticeships !” part. I have been hiring interns for past 5 years and have seen success, catastrophes with the same – it has been mixed bag. But I still strongly believe this is almost the *ONLY* way by which this ecosystem can improve beyond where we manage to float for last half-a-decade or so. I have seen the enthusiasm, fresh ideas that students bring in and if well channelized we can make wonders! Imagine – working in “trenches” solving a critical customer issue and in parallel one can “fork..off” a thread with an intern to explore better solutions – as any Quick solution is almost “dirty” as per experience and statistics. It is in this context I invite final year students to explor...

  Here is a copy-paste of my Twitter updates on recent SVUG Bangalore event. Yes I know it is (was) a bad posting style on newsgroup to do “top-posting” but with new era Twitter-like information sharing, is it that bad? Aren’t people getting used to that style?   Catch me on Twitter @ http://www.twitter.com/sricvc Explaining complex topic such as OVM in 1 hour is hard, more so in post lunch session.. 12:45 AM Nov 11th from mobile web a persistent issue Ive with young AEs - too many usage of superlative language 12:32 AM Nov 11th from mobile web Ashish on OVM intro.. doing a good job 12:25 AM Nov 11th from mobile web the doc from accellera has high level "redirection" session, good stuff.. 12:03 AM Nov 11th from mobile web Dennis on VIP interoperability standard 12:02 AM Nov 11th from mobile web ...

Ajeetha Kumari, CVC Pvt. Ltd. Srinivasan Venkataramanan, CVC Pvt. Ltd. Ramanathan S, Cisco We, just like many other readers of this blog code to make our living . We create, maintain, debug complex SystemVerilog based Verification environments for various design blocks. At CVC one of our specializations is to listen to the tough problems, work with end user to arrive at a solution. Not all the time we get to immediate/magic solutions – we do not claim to have solutions for every problem, but we thrive on such challenges. Specifically Debug is an area that fascinates us much more than anything else! We listen to horror stories of tough debug problems, suggest means of isolating the issues, and suggest better debug hooks for future. We are passionate about emerging technologies and better ways of debug as they evolve. Here is one of them, using VCS’s Aspect Oriented Extensions (AOE) to SystemVerilog to debug a Memory blow-up in SV-TB code. There was a memory-blow up in one of the recentl...

SystemVerilog has a nice implication constraint feature to guard constraint expressions on their applicability. Last week during our SystemVerilog + methodology workshop one of the attendees faced an interesting issue. She was creating a min-VIP for APB as part of our SystemVerilog 10-day workshop (See details at: http://www.cvcblr.com/trng_profiles/CVC_VSV_WK_profile.pdf ). She wrote a APB scenario code that was intended to create a sequence of transactions with varying address, kind etc. Here is a code snippet: constraint cst_xactn_kind{        if(this.scenario_kind == this.sc_id)        this.length == 10;        foreach (items[i])         {           (i==0) -> items[i].apb_op_kind == APB_WR;items[i].addr == 'b01; items[i].wdata == 'd11;  ...

Recent survey from World bank and FICCI finds that only 36% of EMPLOYERS are satisfied with the employability of graduates. A big 64% finds them UNEMPLOYABLE. Read below: New Delhi: A major skill gap exists among Indian engineering graduates, making a strong case for the engineering colleges and institutions to focus more on employability and quality, says a survey. According to the survey, jointly carried out by the Federation of Indian Chambers of Commerce and Industry (FICCI) and the World Bank, 64 percent of surveyed employers are "somewhat", "not very", or "not at all" satisfied with the quality of engineering graduates' skills. The top three most important general skills identified were integrity, reliability and teamwork, while the top three most important specific skills are entrepreneurship, communication in English and use of modern tools and technologies . …. "Most important, graduates have to be able to formul...