CVCBLR's VoW blog - Verification on the Web!

Assertion Based Verification has certainly been one of the mostly debated topics over the last half-a-decade. So much so that one of the past DVCons was full of SystemVerilog & PSL papers on ABV that someone commented it is “ABV conference” than DVCon (was it DVCon 2005?2006?) Even then the adoption rate has been slower than expected – agreed by many stats, EDA folks etc. A relatively new EDA vendor is addressing it via some tools, see: http://www.zocalo-tech.com/index.php   Not clear how easy it will be and how much ROI users will see, but an interesting development I must say. With SystemVerilog 2009 LRM adding checker constructs we predict that the adoption of OVL-like libraries should dramatically improve. We explained it thoroughly in our SVA handbook 2nd edition, see: http://www.cvcblr.com/blog__resources   We have a DVCon 2010 paper on this very topic, see: http://dvcon.org/events/eventdetails.aspx?id=108-3   Let’s see how fast the checker gets imple...

For those of us who have been following the EDA marketing over several years, it is no surprise that there are dedicated marketing professionals within big EDA companies focussing on conveying message/confusing the ecosystem if needed (unfortunately). We have several anecdotes starting from “VHDL is dead” back in 2003 ( http://www.eetimes.eu/uk/17408257 ) and guess what, last month we had a full-house “Advanced VHDL TB class” ( http://www.cvcblr.com/blog/?p=86 ) and another one being scheduled in Jan 2010. I don’t intend to blame any single entity/individual for this, rather this is how it works, and those of us who have seen it for years understand it. Another classical case was for IEEE-1850 PSL – it is alive and kicking with becoming part of recent VHDL as well. Though not much development on PSL itself, but it is expected to stay for much longer than what some folks have predicted. Need a proof – name an EDA vendor without support for PSL – Mentor, Cadence, Synopsys, Aldec – all ha...

Good news for all those Emacs + SystemVerilog users. Puneet has just now released his SV Snippet for Emacs, see: http://coverification.org/2009/12/17/systemverilog-snippets-for-emacs/ Will certainly try it out ASAP. Good start Puneet, keep it up. Thanks for sharing it!

Interesting analysis of how Verification effort is being spent across industry: http://tinyurl.com/dbg-it-man (See the pie-chart, Figure 2). It goes very much inline with what we have been hearing from customers, competitors and also from our own own experience. So DEBUG is THE area if one were to automate within Functional Verification. I’m little surprised to see a 15% spent on ENV – perhaps it is the case for modern SystemVerilog/VMM/OVM stuff, but again that’s for the initial period I suppose. My belief is if you reuse VIPs, leverage on previous code and hire the right candidate, the ENV creation can be handled within 10% The testcase development is shown as 18%, not clear if some of it spread into the coverage bucket (another 15%) – as there is a strong correlation among the two anyway. I believe this is where technologies like Breker’s trek http://www.cvcblr.com/blog/?p=89 becomes interesting.   On the debug – the good old Novas/SpringSoft is still the leader with S...

  In case you missed it: http://chipdesignmag.com/display.php?articleId=3723 I mentioned this during our recent Advanced VHDL TB class during PSL session and attendees were very interested. Today I got a mail back from Chandramohan asking for the link, sent to him and read it once again (must admit, not in full indepth PCI-e level). Overall an excellent paper, perhaps a strong candidate for a DVCon Best paper award – real design bugs/scenarios listed..truly worth reading. Such a nice paper didn’t have to have the following on simulation Simulation, the alternative, brute force approach, ends up wasting resources and introduces additional risk. Even for cases where you think you understand the full state-space, it requires huge effort to develop a test strategy, e.g. complex test scenario with nested loops etc. Manual effort and test are required. Simulation cycles are long and regression test after modifications is slow. Furthermore, the designer generally has to edit do...

OpenSource VMM 1.2 is finally out, see vmmcentral.org – we have been mentioning it to many of our training attendees as “it is coming, it is coming”..now it is HERE!!   One of the greatest challenges we face is when our previous SystemVerilog/VMM attendees attend our newer classes (for upgrade, learn other methodology etc.) – they get very confused about the VMM channel (old way) vs. the new TLM way. The put/get definitions were simple, elegant, ready to use for first timers in VMM 1.0*. True the TLM adds lot of value, but existing users are finding it hard..This is where we folks like CVC fit in I suppose, so no complaints..   Enjoy and welcome the TLM way!

Recently @VGuild Mike asked”   Does anyone use ModelSim's FLI for verification? What are the pros and cons of this? I've been considering adopting SystemVerilog for writing test environments (we code our designs in VHDL and use PSL for assertions and functional coverage) but, from what I can gather, instead of SV I might as well just use ModelSim's FLI and write sophisticated testbenches in C. As an engineer, I am already very familiar with C, and so learning another language for verification (SV) is not desirable. I suppose SV is more portable to other tools, rather than relying on ModelSim's FLI. And I suppose SV is supported by frameworks such as OVM. Other than that, why not use C/C++ as your verification language with the FLI? Though the entire EDA marketing machinery is strongly biased on SystemVerilog, let’s realize that there is a sizeable population using VHDL, C etc. Few pointers for those unconvinced: Our recent VHLD Advanced...

Another piece partly covered in Cooley’s report, but for those interested in full details (more technical updates coming in soon).. Here are my (and my team, who is looking at it closely during an eval) observations on Breker's Trek tool. What we really like about this tool is that it an add-on to any existing methodology/environment (atleast we look at Verilog, SystemVerilog, VMM & OVM for now). Their marketing is also quite good in saying we solve the last 20% of the problem (which usually is the pain-point) though it needs to be proven (our eval is still in early stage). The BNF syntax looks interesting and for the uninitiated it may take a while, but certainly no big deal. We can appreciate the value such a tool brings in for testcase generation. However they claim to be eliminating the need for complex checkers - this is something we are still wary about and would like to delve deep into during the eval. In our view the checker part is hard and will be hard even with Tre...

Some of you might have seen our report of DAC from John Cooley. Here is our full version of NuSym report for those interested. Trek to follow (wiht more updates after the DAC report was sent out).. We at CVC have been tracking Nusym's technology for a while. I visited their booth & demo and here are our (mine combined with my CTO's inputs) comments/impressions. While the generation of additional tests/filling holes is a critical piece of its features, I believe the coverage analysis feature is not so well published/well understood. With our customers who are serious about coverage, the analysis of coverage holes has been one of the biggest pains. The sad part is no major EDA vendor is really adding features to enhance that, with Nusym addressing that problem, it is certainly very useful. The techniques they showed in their slides/demo are not truly path breaking but simple ones that can aid in not wasting time with unreachable coverage holes. It is that simplicity that ...

While there is so much talk about ABV in the market, the adoption is still far less than desired/expected by the buzz! Harry Foster from Mentor tries to find some rationale in his new blog at: http://blogs.mentor.com/verificationhorizons/blog/2009/12/06/abv-and-people-from-missouri/#comment-6   Here is what we from CVC feel about it (also added as comments in that blog). >> What are the obstacles you see to adoption? Major one I hear from RTL folks often is the verbosity associated (as of SystemVerilog 2005) with using OVL-like libraries. Especially existing users of 0-in checkerware are so much pampered by the ease of use and the value it adds - though their management may have the extra $$ as concern - it is hard for them to appreciate the need to type-type-type the “clock, reset” mundane stuff! It was all being “inferred” so far and suddenly come a standard language/implementation such as SVA and that takes them back in history! Refer to AMD’s excellent presentat...

For those who missed it, see: http://www.aldec.in/Company/News.aspx?newsid=34678573-19e6-45a3-99d5-9d5b6accda6c   This is a significant move I would say as it reinforces few facts: Industry is slowly recovering (Hurray!!) India/SouthAsia is gaining more and more importance as a wide customer base – apart from major EDA vendors, others are setting up their own centres, driving investments etc. India as such provides a vibrant FPGA market and there is enough to tap onto it for EDA vendors! Recently Aldec-SA conducted a 2-day seminar on “Creating efficient Testbenches using VHDL”. CVC did the delivery of this seminar, being VHDL & Verification experts.   We got very good feedback from this event, here is a sample: **** Straight from customer ************   Hello Sir, I am Ramesh R Nair, working in Continental Automotive as an ASIC verification engineer as part of my internship programme of M.Tech(VLSI). I have attended your  traini...

As we close on our Advanced VHDL training, some users were wondering if there is an equivalent of SystemVerilog’s always_comb in VHDL. The issue is not about comparing one language with another, rather how to ease the pain of keeping the sensitivity list of a process upto date with design changes. VHDL 2008 allows “all” as sensitivity list in a process. So instead of writing: [cpp] LOG : process(CLK, RESET, SIG1, SIG2, SIG3, SIG4) [/cpp] One can now do: [cpp] LOG : process( all) [/cpp] So happy VHDL coding! On tool support – Anand from my team just now told me Aldec’s Active-HDL supports it. I’m sure there are more tools supporting it too!

Read: http://www.benzinga.com/pressreleases/g50108/magma-announces-talus-design-1-1-and-talus-rtl-1-1-enhanced-synthesis-products- While SV-Design for Synthesis has been talked for a while now, except for some big design houses, we are yet to see full time adaptors. My own experience with SV-Interface synthesis has been bad to say the least – with all extra identifier lengthy names we end up with. Also my suspicion is lack of Formal Verification, Lint and other tool support that makes it even more difficult for Design community. For instance in the above PR, Magma says: Today, most SoC designers use formal verification tools to confirm the final design is equivalent to the source RTL. The process of determining whether identified errors are actual problems often lengthens the design cycle. Talus Design 1.1 and Talus RTL 1.1 include output scripts that simplify and accelerate verification for users of Cadence's industry-leading equivalence checker, Conformal(R). What...

I’ve been impressed by Synopsys’s successful M&A skills – especially leveraging on the proprietary technologies – be it System Science’s Vera (become OpenVera –> SystemVerilog), Co-Design’s SuperLog and now Synplicity’s TotalRecall. http://www.edadesignline.com/showArticle.jhtml?articleID=221901120     Let’s hope to see more this soon

If you have not heard of the buzz word “ABV” (and assuming you are a VLSI front-end engineer of-course) you must be living in a different world I must say (no pun intended) – with so much marketing around it is hard to have missed it – with SystemVerilog Assertions, PSL, OVL etc. Despite that there are some folks who say the adoption is not as much as predicted – heard it from Adam Sherer earlier this week here in Bangalore and now read it on: http://www.edadesignline.com/showArticle.jhtml?articleID=221901260     Well I for one don’t believe this is fully true – atleast in India/AsiaPac – CVC has done well with ABV, we have developed PSL based MIP (Monitor IP) for Taiwan customers, got paid, and delivered several customer trainings on it etc. Though the recent focus has been more on OVM/VMM/VSV – SVA is still making money I must say. It is entering FPGA domain well, see recent ModelsimDE release, Active-HDL supporting ABV for long time now for FPGA domain etc. And just t...

  http://edageek.com/2009/11/16/vhdl-verilog-xilinx-secureip/ Not a bad news after all – given that the industry is showing signs of recovery, such offerings are GREAT indeed – during the downturn several mergers, IP accumulation, consolidation have happened. That might have led to mix of languages in new SoCs. Usually the cost of ownership of a full fledged Mixed-HDL simulator (from any of 3 big EDA vendor) costs a lot (some say a “fortune” though I disagree). But this Riviera offering is certainly encouraging indeed. But is this a “sign-off” tool? Anyone? And BTW – in DAC they announced $1995 package for Active-HDL with similar support, so it is real! http://www.aldec.com/Company/News.aspx?newsid=c86c2ee8-5490-4eae-b61e-a7c0aaf7396c

Read: http://www.your-story.org/eve%E2%80%99s-latest-emulator-offers-the-lowest-cost-of-ownership-in-the-industry-62042/   With the so called “penny-per-gate” pricing – sure is a marketing gimmick, it is becoming more and more viable to explore low cost emulation stuff. We still see that our customers continue to rely on own, self cooked FPGA boards, but with such innovative business models it may be changing soon..   Good job Eve folks – I wonder if they allow sharing “across customers” – say we host one Zebu server at CVC and allow several customers to log-in and pay-per-use!