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In one of our recently concluded UVM training sessions at CVC a customer asked how easy is it to migrate an existing proven code base running with VMM to UVM. Since this is a very common situation, we at CVC have put together a detailed set of case studies and a half-a-day workshop on this topic. As a starting point we ask few simple questions to the customer on their code base so that we can provide an estimated effort involved in the migration. Invariably we start asking “Which VMM version do you run?” – and many are actually unaware :-( Here is a tiny piece of code that would get the answer right from your simulation: A small VMM-built-in utility class is provided as part of VMM named vmm_version . It has few interesting methods, First one being:     The first one displays the major-minor versions such as 1.11 and vendor name. Typically EDA vendors customize these opensource libraries to add debug features and at times to fix incompatibilities across implementations. ...

Recently a customer sought a help on how does the UVM’s built-in scoreboard mechanism works, specifically in_order and algorithmic comparators. While he was able to use them well in his design, it when things fail – i.e. he potentially found a design bug he needed additional assistance in debug. By default the UVM framework provides compare() routine for transaction/ uvm_sequence_item . However unlike its predecessor HVLs such as the “E” language (IEEE 1647) or the OpenVera, System Verilog does not have the compare routine built-in to the language itself (for classes). Hence UVM adds it via base class and more. So when we have a transaction model such as: Now by virtue of inheritance, a handy method my_xactn::compare is available.  So one can use it to compare 2 objects of this type as shown below:   Note: in the above code snippet the return value of compare is unused, in actual code of-course you should assert it/throw an `uvm_error etc. Now, when we simulate this wit...

During our recent SystemVerilog Assertions update webinar ( http://www.cvcblr.com/blog/?p=802 ) one of the audience raised a question on how to check asynchronous events using SVA. Here comes a quick response with code. Also simulated using Aldec’s Riviera-PRO tool.   As you can see in the picture, no clock involved per-se, but use the start and end events themselves as clock for the SVA. So, if you’ve more challenging requirements, do drop in at CVC and we will assist you resolve them! TeamCVC BuzzNet Tags: Verilog , SystemVerilog , SVA , ABV , Aldec , EDA

I am sure you have heard this phrase before – “A sledgehammer to crack a nut”; the below picture describes it all! Would you use a HUGE hammer to crack a small, tiny nut? (If you are further interested in this phrase read: http://www.phrases.org.uk/meanings/sledgehammer-to-crack-a-nut.html ). I recently had a small design error introduced in a piece of  RTL as below: It is an interrupt masking logic, code snippet as below: Note the use of “ANDing” logic – simply, AND- mask with data to produce result .The subtlety in Verilog/System Verilog is that you have 2 seemingly similar operators for doing AND operation; The logical AND: && The bitwise AND: & Given the “loose” data type checking, assignment rules etc. one can get away by using either one of the above many-a-times. In the above case the user used: result = data && mask; With result being a vector the above is a “logical/design error” but usually a Verilog compiler would let this go through (as it is not a...