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Recently one of CVC’s successful alumni, Harshal posted a nice challenge for SystemVerilog newcomers. Harshal has gone through our time trusted, long term SystemVerilog course and got placed at Synopsys and his career has been growing ever since. The original post describing the background is at: http://goo.gl/oq4FmF Crux of it was to “reverse the ordering” or change endianness of a bit stream. While a really rudimentary approach would be to do bit-by-bit as in:   bit [7:0] msb_vec, lsb_vec; msb_vec[7] = lsb_vec[0]; msb_vec[6] = lsb_vec[1]; // … While the above works, it is hard to maintain, upgrade for larger sizes etc. He attempted to automate it using Verilog (V2K)’s bit-slicing as in:   msb_vec [(28-i)] = lsb_vec[(0+(i))-:1]; //Bit Slicing logic But hold on, there is even a smarter way in SystemVerilog, use the “bit streaming” operator: $display (" msb_vec: %b reverse: %b", msb_vec, { << {msb_vec} } ); If the array was unppacked, there is a built-in array.reverse() ...

In one of our recently concluded UVM training sessions at CVC a customer asked how easy is it to migrate an existing proven code base running with VMM to UVM. Since this is a very common situation, we at CVC have put together a detailed set of case studies and a half-a-day workshop on this topic. As a starting point we ask few simple questions to the customer on their code base so that we can provide an estimated effort involved in the migration. Invariably we start asking “Which VMM version do you run?” – and many are actually unaware :-( Here is a tiny piece of code that would get the answer right from your simulation: A small VMM-built-in utility class is provided as part of VMM named vmm_version . It has few interesting methods, First one being:     The first one displays the major-minor versions such as 1.11 and vendor name. Typically EDA vendors customize these opensource libraries to add debug features and at times to fix incompatibilities across implementations. ...

Recently a customer sought a help on how does the UVM’s built-in scoreboard mechanism works, specifically in_order and algorithmic comparators. While he was able to use them well in his design, it when things fail – i.e. he potentially found a design bug he needed additional assistance in debug. By default the UVM framework provides compare() routine for transaction/ uvm_sequence_item . However unlike its predecessor HVLs such as the “E” language (IEEE 1647) or the OpenVera, System Verilog does not have the compare routine built-in to the language itself (for classes). Hence UVM adds it via base class and more. So when we have a transaction model such as: Now by virtue of inheritance, a handy method my_xactn::compare is available.  So one can use it to compare 2 objects of this type as shown below:   Note: in the above code snippet the return value of compare is unused, in actual code of-course you should assert it/throw an `uvm_error etc. Now, when we simulate this wit...

Recently an ABV early stage user/explorer realized it is little hard to get started with OVL-VHDL-Modelsim combination. It surprised us as  it would many others in the industry, having known how well folks at Mentor have been supporting OVL, VHDL etc. As valuable QVP partner with Mentor, we at TeamCVC decided to make it easier for end users. When we dug further we did realize it is not out-of-the-box. Hence we created a quick start example and uploaded it to our website. Feel free to grab it from here: http://www.cvcblr.com/downloads/ovl_vhdl.tgz   It is certainly a quick example just to demo the flow. Will add more soon. Here is the README for the example: CVC's OVL VHDL Example with Modelsim -------------------------------------- To compile and run OVL VHDL example in Questa/MTI follow this example We've used ovl_one_hot on a DUMMY signal, just to demo the flow. You need latest OVL 2.7 release. We've included a part of that in this tar ball To run ---...

Victor Lyuboslavsky, Victor EDA, technology partner, guest blogger at CVC Ever wondered if you can run Verilog Sims from a Web Browser? Well , playing with Verilog and OVL has gotten a little easier recently thanks to the introduction of EDA Playground . EDA Playground is a web application that allows users to edit, simulate, share, and view waves for their HDL code. It is intended to accelerate the learning of design and testbench development with easier code sharing and with simpler access to simulators and libraries. EDA Playground is free , and, since it is web-browser based, it runs on any OS . And you can be up and running in few minutes, without having to install EDA tools, licenses etc. EDA Playground has two editor panes. The left one is intended for testbench code, and the right one intended for design code. The bottom pane is for simulation results, which are updated in real time when the simulation is running. Running a simulation is easy -- select the simulator on the o...

SystemVerilog adds $urandom – a simple random number generator that returns a 32-bit UNSIGNED integer. Contrast it to good old $random – returns a 32-bit SIGNED integer. Consider the below code snippet: integer address; initial begin : b1   address = $urandom;   $display (“%m address: %d”, address); end : b1 When you run the above code in Questa, one in a while you get: # address = 90095195; # address = -949724053; First sight it looks strange, why is $urandom generating a negative number? Bug in the tool? Crazy? (See a real user post at: http://goo.gl/yp0WZ ) A bit of thinking, taking eyes away from monitor screen would help – follow your basics on digital arithmetic: integer – a signed 32-bit number (in Verilog) i.e. holds−2 ( n −1) through 2 ( n −1) −1. (2’s complement representation) So if you assign even a 32-bit UNSIGNED number with the MSB set to 1 – it will be treated as “signed 31-bits” Hence –> $urandom does generate 32-bit UNS...

Sparse arrays in general (in many computer languages) exhibit ‘allocate-on-the-go” behavior. System Verilog is no exception. During today’s VSV training at CVC we had some interesting discussion on this topic. SV assoc-arrays get allocated on-the-go, while it is well known and talked about fact – it is clear for the “write” to array. What about “read”? For some early stage users it is not so obvious that a $display is a reader as well. Consider the following piece of code (full code later): logic [7:0] logic_aa [int]; initial   logic_aa[20] = 121; In the above code the 21st location gets allocated OTG, clear. What about the following? logic [7:0] logic_aa [int]; initial   $display (“%m CVC: read AA: “, logic_aa[20] ); What would you expect? Error? Or allocate OTG? Hold your answer, let’s see full code: Any guess? Well, the $display on an un-allocated assoc-array element is a reader too, hence gets allocated OTG (On-The-Go), default val...

One of the verification related constructs in the vast SystemVerilog language is the program construct. It is also one of the most debated features as to whether it is needed or not. Sure it is very well supported by all EDA tools, and heavily promoted by Synopsys with their VMM to start with. OVM (from Mentor & Cadence) didn’t advocate it though and in fact they discourage it. With UVM – it is a 50-50 – if you like it, use it, else don’t bother. From a technical perspective we at CVC like the fact that we now have a clear TB-2-DUT separation. We do teach this during our regular VSV training sessions ( http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf ). Here comes a 2-minute run-down on this nice feature. Let’s look at some code:   Line 6: #10 DUT ‘reads” a signal named “sig_1”. Line 14: #10 TB “drives” the same signal “sig_1” (They are connected, not shown above) Consider that the above “write” and “read” to the signal were done on “module” scope – t...

Assertions have always been our passion at CVC . The huge marketing buzz around UVM has some impact on how SVA was adopted and talked about at customer sites over last few years. Now that UVM is stable and getting well adopted, users are realizing that assertions play a key role in a UVM env as high quality checkers that can find bugs close to the source of occurrence. Specifically we see more user queries on SVA and training requests on SVA has been on the raise off-late. In one of our recent, part-time SVA training session ( http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf) we had a nice discussion on $rose with a set of enthusiastic attendees. Here is our favorite saying on Assertions: "Things look bright when SVA syntax is discussed. it gets better when we start discussions" One of the nice features in SVA in the ability to detect rising edge with $rose . It is quite simple to understand when applied on single bit signal. For non-startes, it is simp...

It surprises me often how many young engineers (read "fresh graduates/Recent College Graduates") struggle when it comes to the UNIX/GCC/Makefiles etc. I still recall our old IIT days when we did Yahoo/Altavista (Google wasn't around back in 1996) search to resolve most of such issues and of-course use some common sense.  Coming to the recent experience, as we were preparing for our recent demo at SNUG India 2013 DCE booth, I asked some of our young team members to run few UVM tests. When it came to the 11th hour preparations I got several error reports from these young engineers with various errors related to gcc/PATH etc. In our regular UVM training sessions the Makefiles exist so not much challenge in this regard. But when you ask these folks to create Makefile on their own to run UVM, things start getting interesting. A recent error message showed to me was:   recompiling module apb_subsystem_top All of 30 modules done  g++ -w -pipe -O -I/home/student/tools/eda/synops...

SystemVerilog enhances the TEXT-MACRO feature (a.k.a `define-s by many young engineers) of Verilog by a good length. Significant enhancements done are: Added capability to extend the definition to multiple lines Added macros with arguments; Macro arguments can have default values too! (not fully supported by all tools though) However there are few caveats – in general any text-macro usage in any computer language is hard to debug when it fails to compile. So be ready to be patient while debugging macro code. Recently an online forum user asked a question on SystemVerilog macros. Here is what the user defined to start with: To a bare eye, the above looks fine. However a  SV compiler would through an error at it. As per the LRM:   If formal arguments are used, the list of formal argument names shall be enclosed in parentheses following the name of the macro. The left parenthesis shall follow the text macro name immediately, with no space in ...

As many of our customer learn during our regular VSV training sessions , System Verilog added `__FILE__ & `__LINE__ macros similar to C language. It is quite handy for debugging remotely developed code for a newcomer especially. Recently at an UVM forum a user asked how to get the relative path vs. absolute path from this macro. Consider the following code:   The SV LRM says; 22.13 `__FILE__ and `__LINE__ `__FILE__ expands to the name of the current input file, in the form of a string literal. This is the path by which a tool opened the file, So if you provide the absolute path name during compile command, you are bound to get the FULL PATH. Questa when run with full path to the file as below: produces the following output:   And you could get a pretty short output as below if you do a “magic” (Left as exercise to the interested reader :-) ) Enjoy System Verilog and have fun! TeamCVC   Technorati Tags: SystemVeril...

  With one of our recent blog entries on SystemVerilog constraint solver ( http://www.cvcblr.com/blog/?p=725 ) becoming so popular, several readers have contacted us via email to know little more about the puzzle. Specifically they wanted to understand how the solver ordering of variables is determined. Consider the same example as in that previous blog entry: As noted in the previous blog, this creates an “implicit ordering” of variables – i.e. ‘v1” is solved BEFORE “v2”. A smart engineer ( Muthurasu Sivaramakrishnan ) asked this: Nice one. However, why cant we use Solve.. Before constraint in this scenario? The answer is a little involved with yet-another subtlety in the language, and hence this new entry: This reader’s question boils down to whether the above constraint “ cst_ordered” is same as the following; constraint cst_guidance {solve v1 before v2;} First intuition says YES, but the answer unfortunately is NO. In SV there are 2 kinds of solver orde...

As the SVA usage expands/grows in the industry, so do the language syntax/features. One of the recent (2009) addition to System Verilog language was the ability to code “default disabling condition”. It is very handy to have an “inferred” disabling condition for all assertions so that one can save on verbosity while typing – every assertion doesn’t have to repeat;   a_without_default_disable : assert property (disable iff (!rst_n) my_prop); vs. a_with_default_disable : assert property (my_prop); Obviously anything that helps to save some typing is a BOON. However there are some special category of assertions that may get unintentionally disabled by this. For instance the “reset-checks” – assertions that check the reset value of various DUT outputs. For e.g. FIFO empty flag during reset serialout signal from a de-serializer design We recently had a similar DUT being verified with SVA. In the below code, notice the “default disable” and the reset-check...

Are you an avid fan of CRV – Constraint Random Verification? Have you played enough with System Verilog constraints? Many of our customers having attended our regular VSV training ( http://www.cvcblr.com/trainings ) do become so! One of the nice features of SystemVerilog constraint mechanism is its “bi-directionality” – a key feature that makes the distribution fairly wide spread and makes the state space well covered. The industry has learnt it over the last decade of CRV usage – bidirectional constraints are better than unidirectional ones (that was the default in previous generation solver inside popular tool like Specman – called PGen. Even Specman has moved to a more robust, bi-directional IGEN/Intelligen few years back). In SV this bi-directionality is subtle. Consider the code below: To an average SV engineer the above 2 constraints look “same” as the function is trivially doing a return job. However they are different for an avid SV user or a solid SV solver such as...

Recently a user sought to assign a 4-state array (declared as logic ) from the DUT side to a 2-state, bit typed array on TB side. Quite normal and intelligent choice of datatype – as all the TB components at higher level should work on abstract models. However there are 2 important notes – one on the “syntax/semantic” and other on real functional aspect. Focusing on the functional aspect first (as the semantic would be caught by the compiler anyway), what if the DUT signal contained X/Z on the 4-state array value?       When you assign it to the 2-state array counterpart on the TB side – there is information loss and potentially wrong data :-(   Here is where a simple assertion could save hours of debug time for you. Recall that SV has a handy system-function to detect unknown values. One could write a simple assertion using that function at the DUT-TB boundary. See the full code below, with the assertion part highlighted:   With the SVA inc...

  As we wrap up an excellent UVM training for a well informed audience for a local customer at the very beginning of 2013, here is a quick tip for those verification work-horses trying to debug various UVM phase related hangs in their simulations. To be honest, this was developed for another customer way back in the middle of 2012, but never got published, so we decided to do it in early 2013. This is part of our product line where-in we line up various solutions around UVM. The scenario that several customers face is that they have bunch of raise & drop objections, but somehow there is a mismatch of the “raise-to-drop” – i.e. some of the raised objections remained and never got dropped! While UVM comes with few handy plusargs - +UVM_PHASE_TRACE, +UVM_OBJECTION_TRACE etc. these don’t always point you to exact problem, atleast fast-enough. Here is a smarter approach: The uvm_objection base class provides a very nice debug routine named display_objections() . One may want to...

If you are a verification engineer in ASIC/FPGA domain, chances are very little that you have not heard of SystemVerilog. For the last 6+ years it has been making positive impacts to design and verification teams across digital design space. Given this fact, this is no surprise there are several young engineers who jumped on to the bandwagon and picked up the language to a certain level. Many successful engineers in this part of the world have taken CVC ’s VSV course as a wise step towards the same. However when it comes to the production use, plain System Verilog falls behind in certain key areas. Make no mistake, it is a powerful language and is becoming even more powerful with the upcoming 2012 update. See our blog for more on those updates: www.cvcblr.com/blog Many users ask us – why do I need UVM on top of SystemVerilog. While there are ample number of marketing material available on the net for free on this, here is a humble, technical attempt to challenge a solid DV engi...