CVCBLR's VoW blog - Verification on the Web!

Victor Lyuboslavsky, Victor EDA, technology partner, guest blogger at CVC Ever wondered if you can run Verilog Sims from a Web Browser? Well , playing with Verilog and OVL has gotten a little easier recently thanks to the introduction of EDA Playground . EDA Playground is a web application that allows users to edit, simulate, share, and view waves for their HDL code. It is intended to accelerate the learning of design and testbench development with easier code sharing and with simpler access to simulators and libraries. EDA Playground is free , and, since it is web-browser based, it runs on any OS . And you can be up and running in few minutes, without having to install EDA tools, licenses etc. EDA Playground has two editor panes. The left one is intended for testbench code, and the right one intended for design code. The bottom pane is for simulation results, which are updated in real time when the simulation is running. Running a simulation is easy -- select the simulator on the o...

SystemVerilog enhances the TEXT-MACRO feature (a.k.a `define-s by many young engineers) of Verilog by a good length. Significant enhancements done are: Added capability to extend the definition to multiple lines Added macros with arguments; Macro arguments can have default values too! (not fully supported by all tools though) However there are few caveats – in general any text-macro usage in any computer language is hard to debug when it fails to compile. So be ready to be patient while debugging macro code. Recently an online forum user asked a question on SystemVerilog macros. Here is what the user defined to start with: To a bare eye, the above looks fine. However a  SV compiler would through an error at it. As per the LRM:   If formal arguments are used, the list of formal argument names shall be enclosed in parentheses following the name of the macro. The left parenthesis shall follow the text macro name immediately, with no space in ...

Several engineers working and aspiring to work in the field of ASIC front-end design/verification tend to stay away from Verilog’s powerful PLI/VPI – some of them because they see it as old technology and many others – simply “FEAR” from it, thanks to its complex integration with the tools. For those who believe it is old technology – think again, most of the cutting edge EDA innovations (in front end) happening around verification use Verilog’s PLI/VPI to talk to your underlying simulator. To quote a few examples: NextOp /Atrenta’s BugScope   Novas’s Verdi/Debussy Axiom’s @Designer http://www.axiom-da.com (Debugger that can work with all standard Verilog simulators) Trek from Brekersystems ( www.brekersystems.com ) OnPoint from vennsa-da.com Now for those who “fear” from VPI due to its integration challenges – to be fair – you’ve reasons to do so. However advanced functional verification solutions such as VCS, MPSim ( http://www.axiom-da.com ) provide a...

One of the strengths of assertions in SystemVerilog is its well defined sampling semantics. Though it works out-of-the-box and is robust, many users don’t seem to understand it in depth. As we have been blogging on assertions – one needs to be very “pedantic”, i.e. detail oriented to be able to appreciate it, demonstrate it and understand it. We at TeamCVC have been pioneering assertions as a focus area since our PSL book days (end of 2003, http://www.systemverilog.us/psl_info.html ) and it has been almost a decade by now! We cover this in all our training sessions on assertions such as: SVA: http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf PSL: http://www.cvcblr.com/trng_profiles/CVC_LG_PSL_profile.pdf Even during our popular VSV course ( http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf ) we touch upon this topic during the program block discussion. Below is an extract from our training/book on SVA ( http://www.systemverilog.us/sva_info.html ): ...

Last week, our good friend Gaurav Jalan wrote a nice blog at: http://whatisverification.blogspot.in/2012/08/laws-and-verification.html   He has adapted Murphy’s law into Verification as: Applying to Verification ( http://whatisverification.blogspot.in/2012/08/laws-and-verification.html ) Moore’s law – Amount of code to be verified doubles every 2 years. Murphy’s law – Any code that isn’t verified will not work. Now as I recap on last week’s Verilog session delivered to an excited IIT-KGP audience, I realized the same law is applicable to slides/PPT/training too :-) Especially be careful with any code snippet shown in the slides – they  could be wrong – unless verified otherwise ! Now back to the title of this blog entry – what are the differences bet’n Verilog’s $display, $monitor & $strobe ? 1. Usual answer: $monitor is “continuous monitoring” – Yes, good For many fresh graduates the detail stops there – but not for those “verilog hungry, pedanti...

Here is a nice Verilog VPI (Verilog Procedural Interface a.k.a PLI 2.0) app that we mentioned during our just concluded Verilog training at CVC . This application just walks through the complete design hierarchy and spits out the Timescale information for each module. It is quite handy to find which module has the least timescale precision value (and hence controls the whole simulation) for e.g. when the design has been given as a compiled database or a protected one – simple grep/PERL kind of ideas maynot fit. This application will extract: The module name Its Time Scale value Its TimePrecision value Here is a PLI task named " $print_timescale " which if called on a top level module will print this information for the entire hierarchy. The following Verilog code (which could be the top level of your design, or TB) shows how to use such a task.     Needless to say the hierarchy can be very deep and totally encrypted etc. It is all about tr...