Upgrade yourself to SystemVerilog 2012 – our SVA handbook, 3rd edition is published!
They say “ innovation never stops ” – it is true for the SystemVerilog language committee. And it is very true for our co-author Ben Cohen, who even at the retired age keeps updating himself on latest on SV, VMM, OVM, UVM and of-course SVA. Ben Cohen is the Accellera nominated representative for the SV-AC committee on IEEE dev team. See TOC at: http://systemverilog.us/SVA3rdE_preface_toc.pdf The cover of this book is a NASA photograph of Mars, taken by Curiosity. Just like how Mars is enormously big, the verification state space of most of the modern day designs are extremely large. While there have been several advances in the area of "stimulus" or "activation of potential design errors", the amount of checking being done during such activation (either via simulation or formal analysis) demands detailed, precise design specification. This is precisely where SVA fits in the design flow. Just like how the whole world awaits pictures & findings from Curiosity ...