CVCBLR's VoW blog - Verification on the Web!

Several engineers working and aspiring to work in the field of ASIC front-end design/verification tend to stay away from Verilog’s powerful PLI/VPI – some of them because they see it as old technology and many others – simply “FEAR” from it, thanks to its complex integration with the tools. For those who believe it is old technology – think again, most of the cutting edge EDA innovations (in front end) happening around verification use Verilog’s PLI/VPI to talk to your underlying simulator. To quote a few examples: NextOp /Atrenta’s BugScope   Novas’s Verdi/Debussy Axiom’s @Designer http://www.axiom-da.com (Debugger that can work with all standard Verilog simulators) Trek from Brekersystems ( www.brekersystems.com ) OnPoint from vennsa-da.com Now for those who “fear” from VPI due to its integration challenges – to be fair – you’ve reasons to do so. However advanced functional verification solutions such as VCS, MPSim ( http://www.axiom-da.com ) provide a...

Here is a nice Verilog VPI (Verilog Procedural Interface a.k.a PLI 2.0) app that we mentioned during our just concluded Verilog training at CVC . This application just walks through the complete design hierarchy and spits out the Timescale information for each module. It is quite handy to find which module has the least timescale precision value (and hence controls the whole simulation) for e.g. when the design has been given as a compiled database or a protected one – simple grep/PERL kind of ideas maynot fit. This application will extract: The module name Its Time Scale value Its TimePrecision value Here is a PLI task named " $print_timescale " which if called on a top level module will print this information for the entire hierarchy. The following Verilog code (which could be the top level of your design, or TB) shows how to use such a task.     Needless to say the hierarchy can be very deep and totally encrypted etc. It is all about tr...