CVCBLR's VoW blog - Verification on the Web!

At DVCon-14, leading EDA vendor MENT has taken the initiative to propose a Test Specification Standard (see: http://www.goo.gl/BKuNEd ). Given that SV & UVM are well established and deep into their development, stability and adoption phase, the innovation has to come at next level of abstraction. Over the last decade, we at CVC have been working with customers (semiconductor design houses) and EDA partners in defining, evangelizing and deploying multitude of technologies and languages such as OVL, e/Specman, eRM, PSL, SVA, SV, VMM, OVM, AVM, UVM etc. While most of them address the key aspects of "how verification shall be effectively carried out", the next level of "What defines my verification space" has been left for adjacent technologies. Now with this new initiative we are starting to see this problem being addressed. Here is a quick summary of various attempts that have been made to address this problem so far. Hopefully the new Accellera committee will loo...

  Static design verification through thorough RTL analysis started several years ago, with early stage ones simply being “linters” and the later, advanced ones combining some of formal techniques as well. One of the most common complaints by RTL teams while using linters is the SNR – Signal-2-Noise Ratio of the endless set of errors/warnings from the tool. So much so that we have heard of customers giving up on linters, primarily those freebies/bundled with simulator ones. While it is true that some of the reported ones are indeed serious issues, the ROI (Return On Investment) of having RTL designers navigating through the ocean of messages is too little in many cases. OTOH there are clear set of issues that a good LINTer can spot for you quite easily, for instance see: Sledgehammer to crack a nut? – Use right tools for right class of design errors/bugs : http://www.cvcblr.com/blog/?p=377   Essentially it comes to the art of “Finding the needles in the haystack” and in...

To all the ASIC Verification enthusiasts interested in pushing the limits beyond existing languages and methodologies, here is your chance to contribute and be part of the change. As many would be aware, IEEE 1647 standard defines Functional Verification language e . For over a decade e language has provided many advanced features for verification engineers that have recently been adopted to other languages such as SystemVerilog as well. The most recent one being “soft constraints” – see: http://www.cvcblr.com/blog/?p=629   And as more customers demand more features, the working group on e language has been busy adding new proposals. In our last group meeting we agreed on having four working sub-groups. http://www.eda.org/twiki/bin/view.cgi/P1647/Meeting78Minutes These are:- 1)      Temporal Working Group 2)      Messaging Working Group 3)      Types and Operators Working Group 4)    ...

Recently an ABV early stage user/explorer realized it is little hard to get started with OVL-VHDL-Modelsim combination. It surprised us as  it would many others in the industry, having known how well folks at Mentor have been supporting OVL, VHDL etc. As valuable QVP partner with Mentor, we at TeamCVC decided to make it easier for end users. When we dug further we did realize it is not out-of-the-box. Hence we created a quick start example and uploaded it to our website. Feel free to grab it from here: http://www.cvcblr.com/downloads/ovl_vhdl.tgz   It is certainly a quick example just to demo the flow. Will add more soon. Here is the README for the example: CVC's OVL VHDL Example with Modelsim -------------------------------------- To compile and run OVL VHDL example in Questa/MTI follow this example We've used ovl_one_hot on a DUMMY signal, just to demo the flow. You need latest OVL 2.7 release. We've included a part of that in this tar ball To run ---...

For those VHDL folks exploring advanced verification techniques such as ABV (Assertion Based Verification), here is some trick for you all! A many of you would be aware VHDL 2008 standard incorporated IEEE 1850 PSL (VHDL flavor) in it and much before that EDA tools supported PSL + VHDL as a good combination. One of the earliest tutorials on PSL and most widely read one is available @ http://www.project-veripage.com/psl_tutorial_1.php and was authored by our CEO Mrs. Ajeetha Kumari. As it can be seen in the tutorial PSL makes ABV adoption really simple and effective and leads to immediate benefits to the design verification cycle. One of the not-so-uncommon requirements from user community of VJDL + PSL is the ability to refer to PSL events/status from within VHDL Testbench code. This could then be used for PASS/AIL detection, coverage etc. A nice trick in PSL is to use “endpoints”.  Now coming to specific syntax, there are2 variants – in Accellera version of PSL, endpoint was a...

As part of my recent DAC 2013 minutes, here are some of the musings from customer experiences around DAC this year (and some from projects we have been doing in 2012-13 here). While there is a large set of customers exploring SystemVerilog in its full capacity and with UVM, make no mistake - not many will throw away what has been done previously and that was precisely my talking point at DAC 2013 theater presentation earlier this June. Below are some of the slides I presented to get you started: And it is in this context the recently announced UVM-ML initiative from Accellera http://www.accellera.org/apps/org/workgroup/mlwg/ becomes very relevant to every verification team. It is still very much open and all of you can contribute to developing this to be useful to the verification community at large. You can learn more about this UVM-ML from this Cadence blog:  http://bit.ly/14IdjrA See you soon at UVM-ML conference calls/discussions. TeamCVC

As I recount on my recent DAC at Austin experince, one thing that surprised me was the number of Giraffes (sure, images/toys, wish the real ones..but I was at DAC and not a zoo/safari) in the exhibit floor.   Yes, am talking about the Verific's mascot here. It was one of the tallest standing booths so not many could miss it. My friend Sashi Oblisetty led me to them after our early breakfast meeting that morning at DAC. I met with Michiel Ligthart, Verific’s president and chief operating officer. He is a tall man, a Netherlander/Dutch (Graag, ik kan een klien beetje Nederlands spreken .. -  Glad, I can speak a little bit Dutch language, thanks to my early days of work at Philips, Eindhoven). It was a pleasant surprise to see how many customers Verific has to-date, from their facebook page I found: That's impressive indeed. No wonder I found several small Giraffes on other vendors' booth tables. It reminded me of the popular "Intel inside" campaign, perhaps Verific ...

  Over the past few years, the term “pre-silicon verification” has been quite popular and several technology advancements have helped in solving that puzzle. Some of the biggest contributors have been languages such as e /Specman and SystemVerilog with supporting technologies such as constrained-random verification (CRV), coverage-driven verification (CDV) and assertion-based verification (ABV). All these three technologies when used in unison addressed the challenge at the block or intellectual property (IP)level fairly well. Recently UVM has been developed as a framework to use these languages in the best possible manner to try and keep these technologies scalable to larger designs, such as system-on-chips (SoC). Thanks to the Accellera committee devoting time and effort, UVM is becoming quite popular and the de-facto IP verification approach. However with SoCs, there are several new challenges in the verification space that threaten to quickly outgrow the current prevalent t...

As some of our customers ask during our advanced SystemVerilog/UVM training sessions, SystemVerilog doesn’t allow multiple-inheritance. Or to be precise “DID NOT have”, now in SV-2012/2013 it does! For those yet to get there – here is  a quick recap:     Simple inheritance                  Few derived classes             One can of-course “derive” from another “derived class” too, as-in:   This is used widely in good System Verilog code and in general any OOP code. UVM uses this a lot as many of you who have been fortunate to have attended our popular UVM training sessions ( http://www.cvcblr.com/trainings ) across the world (Yes, we have delivered across India, various cities, across the globe as in Europe, Asia etc.). However what was not allowed in older SystemVerilog (2005/2009) is: Multiple inheritance, as in:...

A well known aspect of constraint solving is the ability to classify hard vs. soft constraints. A quick Google search on “soft constraints” would lead you to; http://www.constraintsolving.com/tutorials/soft-constraints-tutorial in case you are interested in theory. Taking a practical example, given the holiday season around the corner many of us would like to travel, book tickets etc. Let’s say that we want to travel from City-1 to City-2 (Say Bangalore to Chennai); the source & destination are fixed and are non-negotiable. But how we travel can be based on preference/availability/cost etc. For instance one may have options of: Flight Bus Train Car Now modeling the above scenario using a constraint specification language like the one in SystemVerilog, there are “constraints” as below; class my_travel_c;   rand places_t src, dst;   rand int cost;   rand travel_mode_t travel_mode;   // Non-negotiable src and dest locati...

They say “ innovation never stops ” – it is true for the SystemVerilog language committee. And it is very true for our co-author Ben Cohen, who even at the retired age keeps updating himself on latest on SV, VMM, OVM, UVM and of-course SVA. Ben Cohen is the Accellera nominated representative for the SV-AC committee on IEEE dev team. See TOC at: http://systemverilog.us/SVA3rdE_preface_toc.pdf The cover of this book is a NASA photograph of Mars, taken by Curiosity. Just like how Mars is enormously big, the verification state space of most of the modern day designs are extremely large. While there have been several advances in the area of "stimulus" or "activation of potential design errors", the amount of checking being done during such activation (either via simulation or formal analysis) demands detailed, precise design specification. This is precisely where SVA fits in the design flow. Just like how the whole world awaits pictures & findings from Curiosity ...

Last week, our good friend Gaurav Jalan wrote a nice blog at: http://whatisverification.blogspot.in/2012/08/laws-and-verification.html   He has adapted Murphy’s law into Verification as: Applying to Verification ( http://whatisverification.blogspot.in/2012/08/laws-and-verification.html ) Moore’s law – Amount of code to be verified doubles every 2 years. Murphy’s law – Any code that isn’t verified will not work. Now as I recap on last week’s Verilog session delivered to an excited IIT-KGP audience, I realized the same law is applicable to slides/PPT/training too :-) Especially be careful with any code snippet shown in the slides – they  could be wrong – unless verified otherwise ! Now back to the title of this blog entry – what are the differences bet’n Verilog’s $display, $monitor & $strobe ? 1. Usual answer: $monitor is “continuous monitoring” – Yes, good For many fresh graduates the detail stops there – but not for those “verilog hungry, pedanti...

This week has been a great start for TeamCVC as we have had one of our best SVA training attendees from a local customer with solid, “pedantic” Design & Verification engineers attending the same. We at CVC cherish challenges and always prefer customers who keep us on our toes (than just a dull set of trainees who sit and “listen” all day along). During some of the advanced SVA part of the slides, we showed the endpoint detection mechanism in SystemVerilog Assertions. To put it simply – an endpoint is an instantaneous result available at every-clock (or sampling event) vs.. a temporal sequence is typically few clocks in length. In what followed as a good discussion we explored various forms of code. Drawn from our popular SVA book (2nd edition, http://www.systemverilog.us/sva_info.html ), here is a slide with code contents.   Alas – we didn’t have a running simulator on the laptop connected to the projector during the training, it became little hard to “visualize” ...

  Earlier this week John’s DeepChip ran a user survey asking for “edgy” questions for DAC-12 “Troublemaker Panel”. Here is what those came out for NextOp were: http://www.deepchip.com/items/0504-05.html >> Yunshan, what does NextOp do and why should users buy your tool? I am amazed at how “basic” some of these “queries” are – aren’t they supposed to be “edgy”? Sure John is doing a great job in publishing “AS-IS”, so can’t blame him for this, it is rather the typical limitation of small start-up, especially in EDA being unable to broadcast its value to masses. Here is my attempt, being a partner, promoter of this technology and SystemVerilog in general. Assume that you are tasked with a I2C IP/sub-system verification (it isn’t that uncommon, is it?). Consider an AMBA based SoC in which this I2C is being integrated, the other side of this IP is typically APB. Your company has tight timelines for this and has provided you VIPs a la modern day UVC (UVM Verification ...

With DAC around the corner, it is time to update our readers on what’s new in Verification in 2012 from EDA perspective. Here is what our TeamCVC have found so far as interesting, will be glad to add more if you drop us a note via info@cvcblr.com or as comments here in this blog itself! Here is an alphabetical order of various vendors & their solutions. AgniSys – your neighborhood automation solution for registers & more If your design is all about IPs and sub-systems with say,more than 50 registers – you would be using one of the several formats (standard/proprietary) to define, maintain and manage the ever changing fields/blocks etc. If you have to manually code these registers in SystemVerilog/VMM/OVM/UVM/eRM – you know how hard it is, how laborious it is and how many hours it consumes to keep them upto-date. This is precisely where AgniSys fits into your flow. Basically their IDesignSpec is a plug-in to Word/XL/FrameMaker etc. to create register specification in ...