CVCBLR's VoW blog - Verification on the Web!

Recently an ABV early stage user/explorer realized it is little hard to get started with OVL-VHDL-Modelsim combination. It surprised us as  it would many others in the industry, having known how well folks at Mentor have been supporting OVL, VHDL etc. As valuable QVP partner with Mentor, we at TeamCVC decided to make it easier for end users. When we dug further we did realize it is not out-of-the-box. Hence we created a quick start example and uploaded it to our website. Feel free to grab it from here: http://www.cvcblr.com/downloads/ovl_vhdl.tgz   It is certainly a quick example just to demo the flow. Will add more soon. Here is the README for the example: CVC's OVL VHDL Example with Modelsim -------------------------------------- To compile and run OVL VHDL example in Questa/MTI follow this example We've used ovl_one_hot on a DUMMY signal, just to demo the flow. You need latest OVL 2.7 release. We've included a part of that in this tar ball To run ---...

For those VHDL folks exploring advanced verification techniques such as ABV (Assertion Based Verification), here is some trick for you all! A many of you would be aware VHDL 2008 standard incorporated IEEE 1850 PSL (VHDL flavor) in it and much before that EDA tools supported PSL + VHDL as a good combination. One of the earliest tutorials on PSL and most widely read one is available @ http://www.project-veripage.com/psl_tutorial_1.php and was authored by our CEO Mrs. Ajeetha Kumari. As it can be seen in the tutorial PSL makes ABV adoption really simple and effective and leads to immediate benefits to the design verification cycle. One of the not-so-uncommon requirements from user community of VJDL + PSL is the ability to refer to PSL events/status from within VHDL Testbench code. This could then be used for PASS/AIL detection, coverage etc. A nice trick in PSL is to use “endpoints”.  Now coming to specific syntax, there are2 variants – in Accellera version of PSL, endpoint was a...

During our recent SystemVerilog Assertions update webinar ( http://www.cvcblr.com/blog/?p=802 ) one of the audience raised a question on how to check asynchronous events using SVA. Here comes a quick response with code. Also simulated using Aldec’s Riviera-PRO tool.   As you can see in the picture, no clock involved per-se, but use the start and end events themselves as clock for the SVA. So, if you’ve more challenging requirements, do drop in at CVC and we will assist you resolve them! TeamCVC BuzzNet Tags: Verilog , SystemVerilog , SVA , ABV , Aldec , EDA

Assertions have always been our passion at CVC . The huge marketing buzz around UVM has some impact on how SVA was adopted and talked about at customer sites over last few years. Now that UVM is stable and getting well adopted, users are realizing that assertions play a key role in a UVM env as high quality checkers that can find bugs close to the source of occurrence. Specifically we see more user queries on SVA and training requests on SVA has been on the raise off-late. In one of our recent, part-time SVA training session ( http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf) we had a nice discussion on $rose with a set of enthusiastic attendees. Here is our favorite saying on Assertions: "Things look bright when SVA syntax is discussed. it gets better when we start discussions" One of the nice features in SVA in the ability to detect rising edge with $rose . It is quite simple to understand when applied on single bit signal. For non-startes, it is simp...

As I recount on my recent DAC at Austin experince, one thing that surprised me was the number of Giraffes (sure, images/toys, wish the real ones..but I was at DAC and not a zoo/safari) in the exhibit floor.   Yes, am talking about the Verific's mascot here. It was one of the tallest standing booths so not many could miss it. My friend Sashi Oblisetty led me to them after our early breakfast meeting that morning at DAC. I met with Michiel Ligthart, Verific’s president and chief operating officer. He is a tall man, a Netherlander/Dutch (Graag, ik kan een klien beetje Nederlands spreken .. -  Glad, I can speak a little bit Dutch language, thanks to my early days of work at Philips, Eindhoven). It was a pleasant surprise to see how many customers Verific has to-date, from their facebook page I found: That's impressive indeed. No wonder I found several small Giraffes on other vendors' booth tables. It reminded me of the popular "Intel inside" campaign, perhaps Verific ...

As the SVA usage expands/grows in the industry, so do the language syntax/features. One of the recent (2009) addition to System Verilog language was the ability to code “default disabling condition”. It is very handy to have an “inferred” disabling condition for all assertions so that one can save on verbosity while typing – every assertion doesn’t have to repeat;   a_without_default_disable : assert property (disable iff (!rst_n) my_prop); vs. a_with_default_disable : assert property (my_prop); Obviously anything that helps to save some typing is a BOON. However there are some special category of assertions that may get unintentionally disabled by this. For instance the “reset-checks” – assertions that check the reset value of various DUT outputs. For e.g. FIFO empty flag during reset serialout signal from a de-serializer design We recently had a similar DUT being verified with SVA. In the below code, notice the “default disable” and the reset-check...

Recently a user sought to assign a 4-state array (declared as logic ) from the DUT side to a 2-state, bit typed array on TB side. Quite normal and intelligent choice of datatype – as all the TB components at higher level should work on abstract models. However there are 2 important notes – one on the “syntax/semantic” and other on real functional aspect. Focusing on the functional aspect first (as the semantic would be caught by the compiler anyway), what if the DUT signal contained X/Z on the 4-state array value?       When you assign it to the 2-state array counterpart on the TB side – there is information loss and potentially wrong data :-(   Here is where a simple assertion could save hours of debug time for you. Recall that SV has a handy system-function to detect unknown values. One could write a simple assertion using that function at the DUT-TB boundary. See the full code below, with the assertion part highlighted:   With the SVA inc...

They say “ innovation never stops ” – it is true for the SystemVerilog language committee. And it is very true for our co-author Ben Cohen, who even at the retired age keeps updating himself on latest on SV, VMM, OVM, UVM and of-course SVA. Ben Cohen is the Accellera nominated representative for the SV-AC committee on IEEE dev team. See TOC at: http://systemverilog.us/SVA3rdE_preface_toc.pdf The cover of this book is a NASA photograph of Mars, taken by Curiosity. Just like how Mars is enormously big, the verification state space of most of the modern day designs are extremely large. While there have been several advances in the area of "stimulus" or "activation of potential design errors", the amount of checking being done during such activation (either via simulation or formal analysis) demands detailed, precise design specification. This is precisely where SVA fits in the design flow. Just like how the whole world awaits pictures & findings from Curiosity ...

One of the strengths of assertions in SystemVerilog is its well defined sampling semantics. Though it works out-of-the-box and is robust, many users don’t seem to understand it in depth. As we have been blogging on assertions – one needs to be very “pedantic”, i.e. detail oriented to be able to appreciate it, demonstrate it and understand it. We at TeamCVC have been pioneering assertions as a focus area since our PSL book days (end of 2003, http://www.systemverilog.us/psl_info.html ) and it has been almost a decade by now! We cover this in all our training sessions on assertions such as: SVA: http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf PSL: http://www.cvcblr.com/trng_profiles/CVC_LG_PSL_profile.pdf Even during our popular VSV course ( http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf ) we touch upon this topic during the program block discussion. Below is an extract from our training/book on SVA ( http://www.systemverilog.us/sva_info.html ): ...

Last week, our good friend Gaurav Jalan wrote a nice blog at: http://whatisverification.blogspot.in/2012/08/laws-and-verification.html   He has adapted Murphy’s law into Verification as: Applying to Verification ( http://whatisverification.blogspot.in/2012/08/laws-and-verification.html ) Moore’s law – Amount of code to be verified doubles every 2 years. Murphy’s law – Any code that isn’t verified will not work. Now as I recap on last week’s Verilog session delivered to an excited IIT-KGP audience, I realized the same law is applicable to slides/PPT/training too :-) Especially be careful with any code snippet shown in the slides – they  could be wrong – unless verified otherwise ! Now back to the title of this blog entry – what are the differences bet’n Verilog’s $display, $monitor & $strobe ? 1. Usual answer: $monitor is “continuous monitoring” – Yes, good For many fresh graduates the detail stops there – but not for those “verilog hungry, pedanti...

This week has been a great start for TeamCVC as we have had one of our best SVA training attendees from a local customer with solid, “pedantic” Design & Verification engineers attending the same. We at CVC cherish challenges and always prefer customers who keep us on our toes (than just a dull set of trainees who sit and “listen” all day along). During some of the advanced SVA part of the slides, we showed the endpoint detection mechanism in SystemVerilog Assertions. To put it simply – an endpoint is an instantaneous result available at every-clock (or sampling event) vs.. a temporal sequence is typically few clocks in length. In what followed as a good discussion we explored various forms of code. Drawn from our popular SVA book (2nd edition, http://www.systemverilog.us/sva_info.html ), here is a slide with code contents.   Alas – we didn’t have a running simulator on the laptop connected to the projector during the training, it became little hard to “visualize” ...

  Earlier this week John’s DeepChip ran a user survey asking for “edgy” questions for DAC-12 “Troublemaker Panel”. Here is what those came out for NextOp were: http://www.deepchip.com/items/0504-05.html >> Yunshan, what does NextOp do and why should users buy your tool? I am amazed at how “basic” some of these “queries” are – aren’t they supposed to be “edgy”? Sure John is doing a great job in publishing “AS-IS”, so can’t blame him for this, it is rather the typical limitation of small start-up, especially in EDA being unable to broadcast its value to masses. Here is my attempt, being a partner, promoter of this technology and SystemVerilog in general. Assume that you are tasked with a I2C IP/sub-system verification (it isn’t that uncommon, is it?). Consider an AMBA based SoC in which this I2C is being integrated, the other side of this IP is typically APB. Your company has tight timelines for this and has provided you VIPs a la modern day UVC (UVM Verification ...