CVCBLR's VoW blog - Verification on the Web!

  Static design verification through thorough RTL analysis started several years ago, with early stage ones simply being “linters” and the later, advanced ones combining some of formal techniques as well. One of the most common complaints by RTL teams while using linters is the SNR – Signal-2-Noise Ratio of the endless set of errors/warnings from the tool. So much so that we have heard of customers giving up on linters, primarily those freebies/bundled with simulator ones. While it is true that some of the reported ones are indeed serious issues, the ROI (Return On Investment) of having RTL designers navigating through the ocean of messages is too little in many cases. OTOH there are clear set of issues that a good LINTer can spot for you quite easily, for instance see: Sledgehammer to crack a nut? – Use right tools for right class of design errors/bugs : http://www.cvcblr.com/blog/?p=377   Essentially it comes to the art of “Finding the needles in the haystack” and in...

As I recount on my recent DAC at Austin experince, one thing that surprised me was the number of Giraffes (sure, images/toys, wish the real ones..but I was at DAC and not a zoo/safari) in the exhibit floor.   Yes, am talking about the Verific's mascot here. It was one of the tallest standing booths so not many could miss it. My friend Sashi Oblisetty led me to them after our early breakfast meeting that morning at DAC. I met with Michiel Ligthart, Verific’s president and chief operating officer. He is a tall man, a Netherlander/Dutch (Graag, ik kan een klien beetje Nederlands spreken .. -  Glad, I can speak a little bit Dutch language, thanks to my early days of work at Philips, Eindhoven). It was a pleasant surprise to see how many customers Verific has to-date, from their facebook page I found: That's impressive indeed. No wonder I found several small Giraffes on other vendors' booth tables. It reminded me of the popular "Intel inside" campaign, perhaps Verific ...

I am sure you have heard this phrase before – “A sledgehammer to crack a nut”; the below picture describes it all! Would you use a HUGE hammer to crack a small, tiny nut? (If you are further interested in this phrase read: http://www.phrases.org.uk/meanings/sledgehammer-to-crack-a-nut.html ). I recently had a small design error introduced in a piece of  RTL as below: It is an interrupt masking logic, code snippet as below: Note the use of “ANDing” logic – simply, AND- mask with data to produce result .The subtlety in Verilog/System Verilog is that you have 2 seemingly similar operators for doing AND operation; The logical AND: && The bitwise AND: & Given the “loose” data type checking, assignment rules etc. one can get away by using either one of the above many-a-times. In the above case the user used: result = data && mask; With result being a vector the above is a “logical/design error” but usually a Verilog compiler would let this go through (as it is not a...