CVCBLR's VoW blog - Verification on the Web!

Recently we were asked a good & interesting question: How do I use "soft constraint" in the macro `uvm_do_with? What would be the syntax? I say this is a good & interesting b'cos of 2 things: 1. The SV LRM doesn't give an explicit example for this (it is fine, not that it should, LRM is not a textbook) 2. The use case should be considered (This specific user had a good need - for automatic coverage closure - or ACC). Now quickly jumping to solution, based on our SystemVerilog 2012 tutorial that our CEO Ajeetha delivered at IIT Mumbai earlier in 2014 ( http://on.fb.me/1yfcBSx ), here is a code snippet: For those who need a quick background on what are soft constraints , see: http://www.cvcblr.com/blog/?p=629   Now with 3 major EDA vendors supporting this syntax, you should leverage on this more!

At DVCon-14, leading EDA vendor MENT has taken the initiative to propose a Test Specification Standard (see: http://www.goo.gl/BKuNEd ). Given that SV & UVM are well established and deep into their development, stability and adoption phase, the innovation has to come at next level of abstraction. Over the last decade, we at CVC have been working with customers (semiconductor design houses) and EDA partners in defining, evangelizing and deploying multitude of technologies and languages such as OVL, e/Specman, eRM, PSL, SVA, SV, VMM, OVM, AVM, UVM etc. While most of them address the key aspects of "how verification shall be effectively carried out", the next level of "What defines my verification space" has been left for adjacent technologies. Now with this new initiative we are starting to see this problem being addressed. Here is a quick summary of various attempts that have been made to address this problem so far. Hopefully the new Accellera committee will loo...

In one of our recently concluded UVM training sessions at CVC a customer asked how easy is it to migrate an existing proven code base running with VMM to UVM. Since this is a very common situation, we at CVC have put together a detailed set of case studies and a half-a-day workshop on this topic. As a starting point we ask few simple questions to the customer on their code base so that we can provide an estimated effort involved in the migration. Invariably we start asking “Which VMM version do you run?” – and many are actually unaware :-( Here is a tiny piece of code that would get the answer right from your simulation: A small VMM-built-in utility class is provided as part of VMM named vmm_version . It has few interesting methods, First one being:     The first one displays the major-minor versions such as 1.11 and vendor name. Typically EDA vendors customize these opensource libraries to add debug features and at times to fix incompatibilities across implementations. ...

Recently a customer sought a help on how does the UVM’s built-in scoreboard mechanism works, specifically in_order and algorithmic comparators. While he was able to use them well in his design, it when things fail – i.e. he potentially found a design bug he needed additional assistance in debug. By default the UVM framework provides compare() routine for transaction/ uvm_sequence_item . However unlike its predecessor HVLs such as the “E” language (IEEE 1647) or the OpenVera, System Verilog does not have the compare routine built-in to the language itself (for classes). Hence UVM adds it via base class and more. So when we have a transaction model such as: Now by virtue of inheritance, a handy method my_xactn::compare is available.  So one can use it to compare 2 objects of this type as shown below:   Note: in the above code snippet the return value of compare is unused, in actual code of-course you should assert it/throw an `uvm_error etc. Now, when we simulate this wit...

One of the verification related constructs in the vast SystemVerilog language is the program construct. It is also one of the most debated features as to whether it is needed or not. Sure it is very well supported by all EDA tools, and heavily promoted by Synopsys with their VMM to start with. OVM (from Mentor & Cadence) didn’t advocate it though and in fact they discourage it. With UVM – it is a 50-50 – if you like it, use it, else don’t bother. From a technical perspective we at CVC like the fact that we now have a clear TB-2-DUT separation. We do teach this during our regular VSV training sessions ( http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf ). Here comes a 2-minute run-down on this nice feature. Let’s look at some code:   Line 6: #10 DUT ‘reads” a signal named “sig_1”. Line 14: #10 TB “drives” the same signal “sig_1” (They are connected, not shown above) Consider that the above “write” and “read” to the signal were done on “module” scope – t...

As part of my recent DAC 2013 minutes, here are some of the musings from customer experiences around DAC this year (and some from projects we have been doing in 2012-13 here). While there is a large set of customers exploring SystemVerilog in its full capacity and with UVM, make no mistake - not many will throw away what has been done previously and that was precisely my talking point at DAC 2013 theater presentation earlier this June. Below are some of the slides I presented to get you started: And it is in this context the recently announced UVM-ML initiative from Accellera http://www.accellera.org/apps/org/workgroup/mlwg/ becomes very relevant to every verification team. It is still very much open and all of you can contribute to developing this to be useful to the verification community at large. You can learn more about this UVM-ML from this Cadence blog:  http://bit.ly/14IdjrA See you soon at UVM-ML conference calls/discussions. TeamCVC

It surprises me often how many young engineers (read "fresh graduates/Recent College Graduates") struggle when it comes to the UNIX/GCC/Makefiles etc. I still recall our old IIT days when we did Yahoo/Altavista (Google wasn't around back in 1996) search to resolve most of such issues and of-course use some common sense.  Coming to the recent experience, as we were preparing for our recent demo at SNUG India 2013 DCE booth, I asked some of our young team members to run few UVM tests. When it came to the 11th hour preparations I got several error reports from these young engineers with various errors related to gcc/PATH etc. In our regular UVM training sessions the Makefiles exist so not much challenge in this regard. But when you ask these folks to create Makefile on their own to run UVM, things start getting interesting. A recent error message showed to me was:   recompiling module apb_subsystem_top All of 30 modules done  g++ -w -pipe -O -I/home/student/tools/eda/synops...

With SystemVerilog language gaining popularity among user, it is getting interesting to see user asking similar/repeating “patterns” of challenges in various forums. One of them is on constraint modeling when it becomes more than simple “a > 10” like stuff. Recently a VerifAcademy user asked:   in my testbench i have to make a random signal "[31:0] distortion". it must contain one (or, in other case, two) hot bit(s) (hot bit is "1", all others are "0"). So i have a problem with writing a constraint: i really don't want to write all possible combinations of these bits (if there are two of them, there will be 32! combinations, so...). Does anyone have solution for this problem?   A smart model is indeed available via 2 features of this vast language – System Verilog: 1. A handy system function to count the number of “ones” 2. Constraints can use functions in expressions. Combining the above two, here is a full solution to the ab...

As many of our customer learn during our regular VSV training sessions , System Verilog added `__FILE__ & `__LINE__ macros similar to C language. It is quite handy for debugging remotely developed code for a newcomer especially. Recently at an UVM forum a user asked how to get the relative path vs. absolute path from this macro. Consider the following code:   The SV LRM says; 22.13 `__FILE__ and `__LINE__ `__FILE__ expands to the name of the current input file, in the form of a string literal. This is the path by which a tool opened the file, So if you provide the absolute path name during compile command, you are bound to get the FULL PATH. Questa when run with full path to the file as below: produces the following output:   And you could get a pretty short output as below if you do a “magic” (Left as exercise to the interested reader :-) ) Enjoy System Verilog and have fun! TeamCVC   Technorati Tags: SystemVeril...

  Over the past few years, the term “pre-silicon verification” has been quite popular and several technology advancements have helped in solving that puzzle. Some of the biggest contributors have been languages such as e /Specman and SystemVerilog with supporting technologies such as constrained-random verification (CRV), coverage-driven verification (CDV) and assertion-based verification (ABV). All these three technologies when used in unison addressed the challenge at the block or intellectual property (IP)level fairly well. Recently UVM has been developed as a framework to use these languages in the best possible manner to try and keep these technologies scalable to larger designs, such as system-on-chips (SoC). Thanks to the Accellera committee devoting time and effort, UVM is becoming quite popular and the de-facto IP verification approach. However with SoCs, there are several new challenges in the verification space that threaten to quickly outgrow the current prevalent t...

  As we wrap up an excellent UVM training for a well informed audience for a local customer at the very beginning of 2013, here is a quick tip for those verification work-horses trying to debug various UVM phase related hangs in their simulations. To be honest, this was developed for another customer way back in the middle of 2012, but never got published, so we decided to do it in early 2013. This is part of our product line where-in we line up various solutions around UVM. The scenario that several customers face is that they have bunch of raise & drop objections, but somehow there is a mismatch of the “raise-to-drop” – i.e. some of the raised objections remained and never got dropped! While UVM comes with few handy plusargs - +UVM_PHASE_TRACE, +UVM_OBJECTION_TRACE etc. these don’t always point you to exact problem, atleast fast-enough. Here is a smarter approach: The uvm_objection base class provides a very nice debug routine named display_objections() . One may want to...

If you are a verification engineer in ASIC/FPGA domain, chances are very little that you have not heard of SystemVerilog. For the last 6+ years it has been making positive impacts to design and verification teams across digital design space. Given this fact, this is no surprise there are several young engineers who jumped on to the bandwagon and picked up the language to a certain level. Many successful engineers in this part of the world have taken CVC ’s VSV course as a wise step towards the same. However when it comes to the production use, plain System Verilog falls behind in certain key areas. Make no mistake, it is a powerful language and is becoming even more powerful with the upcoming 2012 update. See our blog for more on those updates: www.cvcblr.com/blog Many users ask us – why do I need UVM on top of SystemVerilog. While there are ample number of marketing material available on the net for free on this, here is a humble, technical attempt to challenge a solid DV engi...

  UVM Runtime Phasing and Phase Jumping Survey If you are well aware of UVM runtime phasing/phase jumping issues, quickly help yourself and the UVM community at large by filling out this survey: Verilab UVM Phasing Survey Now for a background and for those who are “undecided” whether or not I have an issue with it, here is more information: One of the significant updates done to OVM while bringing up UVM as the standard for verification methodology was the phasing. (For a detailed paper on user issues with OVM phasing approach, see: http://www.synopsys.com/community/snug/india/pages/abstracts.aspx?loc=india&locy=2011 and https://www.synopsys.com/news/pubs/snug/india2011/TA1.2_Intel_paper.pdf ) As with any standard development, there are differing view points coming from various experts, users etc. around the globe.India being the most vibrant Verification geography, it is very probable that many of the verification leads here face these problems day-in and day...

Earlier this week, Simon Segars, EVP & GM Processor and Physical IP Divisions ( http://linkd.in/ThbmbZ ) presented an excellent keynote at an invite-only, executive dinner event around the CDNLive India 2012 http://bit.ly/TxallC organized by Cadence. Our CTO Srini ( http://linkd.in/e6cSbd ) His theme was around the low power requirements in modern mobile devices (understandably, as the market needs this topic and who is in a better position than ARM can talk about this – being at the center of most of those smartphones!) In a well drafted, upto-the-point, picture-centric presentation Simon did a great job of explaining what ARM’s big.LIITLE architecture is all about! As of today, ARM provides Cortex A-15 like cores for the high-end devices:   Quickly ARM realized there is a strong need for low-energy, low-cost cores too to serve the entry level smartphones – here comes the ARM Cortex A-7   Now with lot of data mining and analysis Simon showed a typical...

One of the strengths of assertions in SystemVerilog is its well defined sampling semantics. Though it works out-of-the-box and is robust, many users don’t seem to understand it in depth. As we have been blogging on assertions – one needs to be very “pedantic”, i.e. detail oriented to be able to appreciate it, demonstrate it and understand it. We at TeamCVC have been pioneering assertions as a focus area since our PSL book days (end of 2003, http://www.systemverilog.us/psl_info.html ) and it has been almost a decade by now! We cover this in all our training sessions on assertions such as: SVA: http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf PSL: http://www.cvcblr.com/trng_profiles/CVC_LG_PSL_profile.pdf Even during our popular VSV course ( http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf ) we touch upon this topic during the program block discussion. Below is an extract from our training/book on SVA ( http://www.systemverilog.us/sva_info.html ): ...

  CVC to highlight UVM training, methodology consulting, auditing & debug capabilities at SNUG India Designer Community Expo Bangalore, India , June 13, 2012 – CVC Pvt. Ltd., provider of the industry’s most advanced functional verification training solutions, today announced that it will be participating in the Synopsys Users Group (SNUG) Designer Community Expo (DCE) Wednesday, June 13, booth #200 in the IC Verification community. UnleashingUVM™ is CVC’s series of solutions centered around Universal Verification Methodology (UVM). It brings in range of training tailored to different end-users such as IP verification environment developers, VIP users and SoC integrators. It also comprises of UVM debug utilities, UVM rules/guidelines, a comprehensive auditing for UVM compliance leading to higher verification quality. The SNUG Designer Community Expo (DCE) is a unique networking event featuring Synopsys and its ecosystem partners from across the electronics industry. A...