CVCBLR's VoW blog - Verification on the Web!

As a sub-thread of a core technical discussion, Alan Fitch from UK brought up an important question: See the full thread (more technical @: http://www.verificationguild.com/modules.php?name=Forums&file=viewtopic&p=16440#16440   Alan Fitch writes: I agree with your answer, but as a pedantic engineer (is there any other sort?)  I really wish there isn't any other - but not sure if many young engineers agree with that. BTW I do consider myself young, am really talking about fresh/beginners/early career folks. I see some degradation on that side, I was at KCG Tech ( http://www.kcgcollege.com/ ) this weekend for their NCV09 conference. We from CVC were  delivering our VoW tutorial series on "Functional Verification methodology", and also a case study on Assertion-Based Verification by Thirumalaiprabhu, my colleague @CVC. I met with the teaching staff there. Had a long chat on this very topic - the fresh graduates recently aren't pedantic - atle...

16 Aug 2009: http://www.livemint.com/2009/08/16131752/Corporate-India-resumes-hiring.html?h=A1 This is a very refreshing read indeed and inline with CVC’s prediction on the market. It is very important not to jump too many steps too fast and call it honky-dory, it is essential that we stay on the floor, do the basics and get the ecosystem back on track. For fresh graduates this is an ideal opportunity to acquire right skills needed in the industry and not fall prey to “name-sake” trainings. Start with “END” in mind – ask the right set of questions; ensure you have confidence in the team that you would work with during a training/incubation to see that your career is being built and not just a set of language skills.   For recently displaced workers – this is better than ever time to hone their skills to grab the opportunities as they open up locally, slowly. Do not rely just on openings at job-portals. For the past 6 months we at CVC have been assisting various VLSI compan...

1-day course on “Do-it Right – Advanced VMM” …SystemVerilog framework for creating effective Verification Environment CVC (www.cvcblr.com) is announcing a new session of its 1-day course on “Do-it Right – Advanced VMM” including new base classes and RAL . Duration Topic Duration Advanced VMM 1 day The course is structured in a balanced manner with theory and lab sessions tightly embedded in a manner that helps in mastering topics learned so far in the course. Schedule: August 19 th at Bangalore To attend this class, confirm your registration by sending an email to training @ cvcblr.com Ph: +91-9916176014, +91-80-42134156 Please include the following details in your email: Name: Company Name: Contact Email ID: Contact Number:

2-days course on “Do-it Right – Basic VMM” …SystemVerilog framework for creating effective Verification Environment CVC (www.cvcblr.com) is announcing a new session of its 2-days course on “Do-it Right – Basic VMM” - a step-by-step guide to building scalable, reusable and flexible Verification Environment using VMM. Duration Topic Duration Quick SystemVerilog refresh 0.5 day Verification Methodology 1.5 days The course is structured in a balanced manner with theory and lab sessions tightly embedded in a manner that helps in mastering topics learned so far in the course. Schedule: August 12 th ,13 th at Bangalore To attend this class, confirm your registration by sending an email to training @ cvcblr.com Ph: +91-9916176014, +91-80-42134156 Please include the following details in your email...

As a quick update to ACC post, VCS’s 2009.06 has come out with a related technology called Coverage Convergence Technology (CCT) , read a user success at: Improve Verification Productivity with Synopsys Coverage Convergence Technology   And NuSym rocks as ever before in this domain with great user interest for the successive DAC. They seem to have a good technology, but my worry is will the customers pay extra $$$$ for it? Let’s wait and watch. But their technology as can be read from their WhitePaper is based on “Path Tracing” and sounds very solid. The real challenge is in “execution” – or implementing that technology in a solid code in an EDA tool. Perhaps if you have few Armenian folks (who wrote the code for Synopsys’s new “Custom Designer” product), that will help? – A separate entry on that product soon..   Srini

Migrating my old blog post to CVC’s homepage. Tune-in for an update (with DAC09 underway, didn’t you expect that anyway :-) ??)   Automatic Coverage Closure – my perspective Recently EDA tools are emerging in the area of “Automatic Coverage Closure” that promise a new level of automation in CDV/MDV/any_other_Buzz_word_Driven_Verification process. A significant name in this arena is nuSym, a relatively new EDA player. There have been few good reviews about them @ Deepchip.com. http://deepchip.com/items/0479-05.html http://deepchip.com/items/0473-06.html http://deepchip.com/items/dvcon07-06.html And another one @ SiliconIndia: http://www.siliconindia.com/magazine/articledesc.php?articleid=DPEW289996212 And very recently on VerifGuild: http://www.verificationguild.com/modules.php?name=Forums&file=viewtopic&t=3102 I like Gopi’s post/comment b’cos I have the same opinion about CRV (Constraint Random Verification) – it catches scenarios/bugs that you didn’t envision – either via cons...