CVCBLR's VoW blog - Verification on the Web!

Based on DVCon 2010 paper on SystemVerilog Assertions - 2009 (see www.cvcblr.com --> Publications) we recently got our FIFO model run through NextOp's BugScope tool. It produced some interesting stuff. The main one I liked is pop |-> full; This is an eye opener property - as this should never be the case! But BugScope indeed indicated that we are missing this - either as assert or cover. Obviously this is not a good assert, so when we analyzed deep, it turned out to be a "valid coverage" based on the RTL written. Details at: http://verificationguild.com/modules.php?name=Forums&file=viewtopic&p=18073#18073 So essentially we did have a coverage hole - when that hole is analyzed, we get a design error/bug! What an interesting go-around way of detecting bugs - who cares, as long the bug detection is automatic, it is good! Ajeetha, www.cvcblr.com

That could be a killer combination for specific functional verification goals. For instance look at recent SNPS's webinar on MVRC & Formality @ http://bit.ly/9oupo9 Other ideas I have on using Formal equiv checker in functional verification are to automate Gate Level debug, debugging X's, porting RTL TB's to GLS etc. Need a good API + formal tool for all those ideas though... Signing off! www.cvcblr.com

For all those System Verilog geeks, lovers, followers here is a sigh of BIG relief - at last we have a UNIVERSAL Verification Methodology that all the 3 major EDA vendors would openly support (and hopefully promote as well). As we speak, UVM-EA (Early Adaptor) release is now available. Take a look at it from Accellera site . CVC ( www.cvcblr.com ) has been constantly following this release and are about to release our fresh trainings on this UVM. After all it is based on OVM 2.0.* on which we had successful trainings delivered to several customers locally. The most recent one just over the last weekend! (Yeah, we do have weekend classes as well). So, what are you waiting for? Go ahead and ask for our upcoming UVM class via training@cvcblr.com or call us via +91-9620209226 Talk to you soon on UVM! CVC Team www.cvcblr.com

Hello, Queues in SV provide more search related functions such as "find_first/find_index" etc. that aid in scoreboard modeling. It is true that assoc-arrays are slightly better at memory foot-print. Also indexing can be done via any field there, not in Q - but in Q one can use the "find_first..with" to do the same. As you can see above - this debate is meaningless after a point (as our friend Keith/Metta pointed out nicely) - you use what is easy for you. Another aspect to consider is tool support. As of today I'm aware of 4 EDA tools nicely support Qs, few have issues/limitations with assoc-arrays though. So check your tool doc too before you make a choice. Regards Srini www.cvcblr.com --- In ASICDESIGN@yahoogroups.com, Cool Cake <cool_cake20@...> wrote: > > > Hi, > >         For this question , they posted answer as "queues" in a website.But I think associative array's are better suite in building score board.Because indexing...

Many have asked us the following: Is CVC a training company? I see: www.cvcblr.com/trainings Do you work on “live” projects? What is your TDG really doing? and more. Usually these questions are more from students/RCGs (Recent College Graduates) than the experienced lot – as the experienced lot is well networked with CVC founders ( www.linkedin.com/in/svenka3 , www.linkedin.com/in/ajeetha ) and can hence know about us well. Our honest answer to such questions is “all of the above” :-) That’s YES, we ARE proud to be a training company www.cvcblr.com/trainings – simply b’cos we know why we are doing that. We work on “live” projects – we constantly upgrade to next generation technology, the most recent being the SystemVerilog VMM/OVM, Low power etc. What makes us really different and keeps us constantly innovating is the thirst for “doing better”. This is the core of our PDG – Product Development Group (yet to be formally announced on our website), we look for ways to enhance the pr...

             Verifying SoC is fun and tedious. Especially with several buzz words around the corner, it is quite easy to get lost in maze of buzz-words and miss the goal. At the end one may feel that the plain old wisdom of whiteboard based testcase review/plan is/was lot more controllable & observable. We did that back in 2000 @ Realchip communications and yes it worked really well. But with shrinking times and mounting complexity is that really fast enough? Before I hear constrained-random, blink for a while – how much random do you want your end-to-end data flow in-and-out of ASIC/SoC to be? We at CVC ( www.cvcblr.com ) take pride in partnering with all major EDA vendors ( http://www.cvcblr.com/partners ) – big & small to look for best possible solution for different problems than suggesting “one-size-fit-all” like solution. Here is a relevant thread @Vguild: http://www.verificationguild.com/modules.php?name=Forums...

  In case you missed it, read a user report on NextOp’s technology at: http://www.deepchip.com/items/0484-01.html   In next couple of blog entries, I will share my reading, reflections on this detailed report. To start with, this technology seems to address some of the “points to ponder” being discussed at: http://www.cvcblr.com/blog/?p=146   As there is no whitepaper/material available on this technology I base my reflections solely on the ESNUG report. First thing that strikes me is, it seems to suggest in identifying “what assertions to write”. But then it takes a radically different approach to this problem atleast from what has been attempted so far by other EDA vendors. The single most difference is it takes the RTL + Testbench as guide to create assertions/properties. From the report: BugScope takes in our RTL design and testbench as inputs and generates properties, (which we then categorize as assertions or coverages) that help identify bugs and cove...