CVCBLR's VoW blog - Verification on the Web!

Clifford Cummings ( http://www.linkedin.com/in/cliffcummings ) is a crowd puller – no doubt. Consider: Hot summer mid-day (2 PM start time) Bangalore traffic/center of city (potential peak traffic towards end time of 5.30 PM) A venue known/infamous for a “HUGE” area but no so frequented by hi-tech community of Silicon Valley of India, past events over there had history of terrible attendance Yet there were close to 70+ Verification engineers at Cliff’s UVM/OVM seminar aptly titled as: “Advanced SystemVerilog Tips Including OVM & UVM Tips”   It was indeed for Advanced System Verilog users as he had most of the slides on OVM/UVM. TeamCVC ( http://in.linkedin.com/in/cvcblr ) specifically its trainees, some 11 of them were there cherishing their stint at CVC ( www.cvcblr.com ) as they hear a world-class seminar and being a fresh graduate, making sense out of that was  a pride on its own. That’s the power of CVC’s time proven EIC training ( http://www.cvcb...

The Accellera technical subcommittee to develop a tagging standard for soft IP tagging is currently being formed.  The first meeting will be held via teleconference, followed by an open Birds of a Feather session at DAC. Any interested parties are invited to join and participate. This group will develop a standard to support the tracking of soft design IP through the development process such that it can be readily identified in a final GDSII database.  This facilitates a data-driven method to track IP “where used” for applications such as ownership, royalty calculations and recognition, implemented version identification for applicable bug fixes and errata, among others.  The work will align with the VSIA-developed Virtual Component Identification Physical Tagging Standard (Hard IP TaggingStandard), and will evaluate and update the Virtual Component Identification Soft IP Tagging Standard to reflect this new usage paradigm. The first working group meeting will be hel...

If you are curious about recently released UVM standard – you won’t have missed to note the DVCon-2011 blogs/tweets etc. Some of those captures can be seen at http://www.cvcblr.com/blog/?p=283   http://www.cvcblr.com/blog/?p=298 http://www.cvcblr.com/blog/?p=322 Now, in case you didn’t visit DVCon, here is UVM coming to YOU – at Bangalore & Pune. Thanks to Cadence & QLogic, there are free UVM update events being scheduled on Apr 13th & Apr 19th. Register for free right away. Agenda: New UVM 1.0 overview and comparison to OVM Important OVM and UVM phasing Secrets in mastering OVM and UVM Graceful termination of tests in OVM and UVM with emphasis on the objection mechanism Some of Cliff's favorite SystemVerilog tips and tricks Some early UVM techniques and best practices Date Time Location April 13, Wednesday 2.00pm – 5.30pm Bangalore Audito...

Last week TeamCVC held a 4-day training on System Verilog at Pune – a pleasant city in the western ghats of India, also known as the "Oxford of the East" due to its vast student community & research institutions. TeamCVC has been to Pune few years back for a VMM training, see some of those experiences at http://bit.ly/eHMaH7 But this visit has shown how fast this city has been growing and the recent boom it has been experiencing - atleast through an entrepreneur viewpoint. The first thing that struck me on my way to the hotel from airport was the flurry of developments – almost 90% of all hoarding/banners showing upcoming apartments, It is almost like Bangalore some 10 years back – with so many IT firms growing their staff strength, new office spaces being built etc. The weather was pleasant, gets quite hot mid-day but then cool breeze in the evening, gets little cold during early mornings. Kind of similar to Bangalore, atleast for this period of the year. The Hinjewad...

Last week at DVCon we had a very interesting Birds-of-a-Feather meeting on Mar 1st evening. Panelists included Tom Anderson from Cadence , Yunshan Zhu from NextOp and Adnan Hamid from Breker Systems .   It was moderated by Srinivasan Venkataramanan from CVC . See pre-BoF invite/details at: http://www.cvcblr.com/blog/?p=272 The theme of this panel was “Verification Closure” – given that 2011 DVCon marked the birth/release of UVM standard for developing reusable, inter-operable VIPs, it was a perfect fit for a group of technocrats to explore what is beyond UVM. We had some very interesting discussions and here are some excerpts. If you feel I missed some discussion topic or have any comment on this, feel free to blog it here! To start with, Rick Nordin of Breker Systems introduced the panel topic and the moderator. Srini ( www.linkedin.com/in/svenka3 ) presented single slide setting the stage for the panelists and had the honor of introducing the esteemed panel...

Here are some snaps from recent DVCon UVM poster session. More than 12 vendors demonstrated their commerical offerings around UVM and it was an electrifying experience for the attendees/potential customers (some 180+ UVM tutorial attendees). Products/offerings broadly fell in the following categories: Simulators – Cadence, Synopsys (DOn’t recall Mentor on poster, but of-course Questa supports UVM), another missing poster EDA tool company was Aldec. Though both Mentor & Aldec had their booths at the exhibit. Cadence had a poster on how IUS supports UVM and extended debug features targeted for UVM users. Here is Joesph H with his Cadence poster     Synopsys had a clear, simple poster on how VCS extends its leadership in SystemVerilog performance. Here is Adiel Khan explaining with passion to a customer Synopsys poster:   Register model automation, maintenance: AgniSys dominated the poster with lots of visitors asking questions. Infact their poster a...

At DVCon Accellera released its latest standard for VIP interoperability named UVM – Universal Verification Methodology. 12+ vendors demonstrated their commercial solutions around UVM – hasn’t happened for a long time in the industry around single standard – except perhaps for SystemVerilog itself (back in 2003?) While the technical details can be talked for very long time, here is a practical, real-life experience of “waiting for too long to have this standard”. This could be your simple means of convincing your technical management why they should be looking at UVM seriously in next project. On the DVCon evening (Mar 1st) I was having dinner with a good old friend of mine, Mahesh. Here are his experiences/pains of working with various verification projects for the past 6+ years: Mahesh – it was a nightmare 5-6 years ago for Verification engineers – you move from one project to another within the SAME company (for instance acquired companies in a large company), your way ...