CVCBLR's VoW blog - Verification on the Web!

Samurai is a hard hitting warrior with never-say-die attitude. So far as Debug is concerned, the verification engineers become Samurai especially when it comes to Gate Level Debug with timing violations. Here is a breather for those non-Samurai s class of engineers coming to you from an advanced Debug integration in Mentor’s Questa debug platform ! If you have been through GLS (Gate Level Simulation) – you are sure of this topic; If you are a honest individual you would admit it is one of the most dreaded debug issues that you see in your DV life! When those timing violations appear here is what w do: Go over the library files to locate the $setp/$hold specifications, Occasional LRM reading to recall the arguments to those system tasks Decipher the specparam value (recall it could be a complex expression involving other specparam, parameters, `define – and last but not the least, any SDF overrides via LABEL) Now once you have this so called “static” information, t...

They say “ innovation never stops ” – it is true for the SystemVerilog language committee. And it is very true for our co-author Ben Cohen, who even at the retired age keeps updating himself on latest on SV, VMM, OVM, UVM and of-course SVA. Ben Cohen is the Accellera nominated representative for the SV-AC committee on IEEE dev team. See TOC at: http://systemverilog.us/SVA3rdE_preface_toc.pdf The cover of this book is a NASA photograph of Mars, taken by Curiosity. Just like how Mars is enormously big, the verification state space of most of the modern day designs are extremely large. While there have been several advances in the area of "stimulus" or "activation of potential design errors", the amount of checking being done during such activation (either via simulation or formal analysis) demands detailed, precise design specification. This is precisely where SVA fits in the design flow. Just like how the whole world awaits pictures & findings from Curiosity ...

One of the strengths of assertions in SystemVerilog is its well defined sampling semantics. Though it works out-of-the-box and is robust, many users don’t seem to understand it in depth. As we have been blogging on assertions – one needs to be very “pedantic”, i.e. detail oriented to be able to appreciate it, demonstrate it and understand it. We at TeamCVC have been pioneering assertions as a focus area since our PSL book days (end of 2003, http://www.systemverilog.us/psl_info.html ) and it has been almost a decade by now! We cover this in all our training sessions on assertions such as: SVA: http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf PSL: http://www.cvcblr.com/trng_profiles/CVC_LG_PSL_profile.pdf Even during our popular VSV course ( http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf ) we touch upon this topic during the program block discussion. Below is an extract from our training/book on SVA ( http://www.systemverilog.us/sva_info.html ): ...

Last week, our good friend Gaurav Jalan wrote a nice blog at: http://whatisverification.blogspot.in/2012/08/laws-and-verification.html   He has adapted Murphy’s law into Verification as: Applying to Verification ( http://whatisverification.blogspot.in/2012/08/laws-and-verification.html ) Moore’s law – Amount of code to be verified doubles every 2 years. Murphy’s law – Any code that isn’t verified will not work. Now as I recap on last week’s Verilog session delivered to an excited IIT-KGP audience, I realized the same law is applicable to slides/PPT/training too :-) Especially be careful with any code snippet shown in the slides – they  could be wrong – unless verified otherwise ! Now back to the title of this blog entry – what are the differences bet’n Verilog’s $display, $monitor & $strobe ? 1. Usual answer: $monitor is “continuous monitoring” – Yes, good For many fresh graduates the detail stops there – but not for those “verilog hungry, pedanti...

Here is a nice Verilog VPI (Verilog Procedural Interface a.k.a PLI 2.0) app that we mentioned during our just concluded Verilog training at CVC . This application just walks through the complete design hierarchy and spits out the Timescale information for each module. It is quite handy to find which module has the least timescale precision value (and hence controls the whole simulation) for e.g. when the design has been given as a compiled database or a protected one – simple grep/PERL kind of ideas maynot fit. This application will extract: The module name Its Time Scale value Its TimePrecision value Here is a PLI task named " $print_timescale " which if called on a top level module will print this information for the entire hierarchy. The following Verilog code (which could be the top level of your design, or TB) shows how to use such a task.     Needless to say the hierarchy can be very deep and totally encrypted etc. It is all about tr...

This week has been a great start for TeamCVC as we have had one of our best SVA training attendees from a local customer with solid, “pedantic” Design & Verification engineers attending the same. We at CVC cherish challenges and always prefer customers who keep us on our toes (than just a dull set of trainees who sit and “listen” all day along). During some of the advanced SVA part of the slides, we showed the endpoint detection mechanism in SystemVerilog Assertions. To put it simply – an endpoint is an instantaneous result available at every-clock (or sampling event) vs.. a temporal sequence is typically few clocks in length. In what followed as a good discussion we explored various forms of code. Drawn from our popular SVA book (2nd edition, http://www.systemverilog.us/sva_info.html ), here is a slide with code contents.   Alas – we didn’t have a running simulator on the laptop connected to the projector during the training, it became little hard to “visualize” ...

  During this week’s SystemVerilog training, a smart engineer, Sarvendranath created an interesting “derived” example from our regular lab code. After all an engineer is supposed to be “Pedantic” (See an interesting side post on this at: http://www.cvcblr.com/blog/?p=14 ). The topic under discussion was arrays and out-of-bound accesses. This has been talked in detail at various websites for C++ etc. as in: http://w3.ualg.pt/~pjotr/Lectures/PI/WWW/t13.html   Consider the below code snippet:       The array has 3 unpacked dimensions with bounds at 2,3,4. The “in-bound access” shall be “0..1”, “0..2” and “0..3”. Now what happened during a lab trial was to use an incorrect for loop a shown above with the loop count running from “1..2”, “1..3”, and “1..4” –> The last index has been out-of-bound. Going by several implementation discussions, many tools will not flag this (unfortunately) as it needs to optimize for “performance” and these kind of check...