CVCBLR's VoW blog - Verification on the Web!

  For those uninitiated with the DITL, here is a quick 101 on DITL: – what do you do on a typical day? That’s your Day-in-The-Life   Now to relate it to our VoW blog ( www.cvcblr.com/blog ), here is how a DITL for verification could be nicely defined, thanks to Dave Fechser of LSI, read his excellent article on Design Specification Requirements with Verification in Mind at: http://bit.ly/J6Jswr We at CVC follow this DITL model a lot during our training sessions especially for fresh graduates (See: http://goo.gl/aU8k2 for a PPT and download the contents from: http://www.cvcblr.com/trng_profiles/CVC_EIC_profile.pdf ) Earlier this week, Simon Segars, EVP & GM Processor and Physical IP Divisions ( www.linkedin.com/pub/simon-segars/2/2a0/556 ) presented an excellent keynote at an invite-only, executive dinner event around the CDNLive India 2012 http://bit.ly/TxallC organized by Cadence. His theme was around the low power requirements in modern mobile devices ...

Earlier this week, Simon Segars, EVP & GM Processor and Physical IP Divisions ( www.linkedin.com/pub/simon-segars/2/2a0/556 ) presented an excellent keynote at an invite-only, executive dinner event around the CDNLive India 2012 http://bit.ly/TxallC organized by Cadence. His theme was around the low power requirements in modern mobile devices (understandably, as the market needs this topic and who is in a better position than ARM can talk about this – being at the center of most of those smartphones!) One of the most interesting parts of his keyonte was the smartphone market segmentation he showed. IIRC (If I Remember Correctly), this was  Gartner backed market estimates/data on how the smartphone market is evolving in the near future. While several enthusiasts around the world are going gangnam about the new iPhone5 which is a high-end smartphone,                     He show...

Earlier this week, Simon Segars, EVP & GM Processor and Physical IP Divisions ( http://linkd.in/ThbmbZ ) presented an excellent keynote at an invite-only, executive dinner event around the CDNLive India 2012 http://bit.ly/TxallC organized by Cadence. Our CTO Srini ( http://linkd.in/e6cSbd ) His theme was around the low power requirements in modern mobile devices (understandably, as the market needs this topic and who is in a better position than ARM can talk about this – being at the center of most of those smartphones!) In a well drafted, upto-the-point, picture-centric presentation Simon did a great job of explaining what ARM’s big.LIITLE architecture is all about! As of today, ARM provides Cortex A-15 like cores for the high-end devices:   Quickly ARM realized there is a strong need for low-energy, low-cost cores too to serve the entry level smartphones – here comes the ARM Cortex A-7   Now with lot of data mining and analysis Simon showed a typical...

Samurai is a hard hitting warrior with never-say-die attitude. So far as Debug is concerned, the verification engineers become Samurai especially when it comes to Gate Level Debug with timing violations. Here is a breather for those non-Samurai s class of engineers coming to you from an advanced Debug integration in Mentor’s Questa debug platform ! If you have been through GLS (Gate Level Simulation) – you are sure of this topic; If you are a honest individual you would admit it is one of the most dreaded debug issues that you see in your DV life! When those timing violations appear here is what w do: Go over the library files to locate the $setp/$hold specifications, Occasional LRM reading to recall the arguments to those system tasks Decipher the specparam value (recall it could be a complex expression involving other specparam, parameters, `define – and last but not the least, any SDF overrides via LABEL) Now once you have this so called “static” information, t...

They say “ innovation never stops ” – it is true for the SystemVerilog language committee. And it is very true for our co-author Ben Cohen, who even at the retired age keeps updating himself on latest on SV, VMM, OVM, UVM and of-course SVA. Ben Cohen is the Accellera nominated representative for the SV-AC committee on IEEE dev team. See TOC at: http://systemverilog.us/SVA3rdE_preface_toc.pdf The cover of this book is a NASA photograph of Mars, taken by Curiosity. Just like how Mars is enormously big, the verification state space of most of the modern day designs are extremely large. While there have been several advances in the area of "stimulus" or "activation of potential design errors", the amount of checking being done during such activation (either via simulation or formal analysis) demands detailed, precise design specification. This is precisely where SVA fits in the design flow. Just like how the whole world awaits pictures & findings from Curiosity ...

One of the strengths of assertions in SystemVerilog is its well defined sampling semantics. Though it works out-of-the-box and is robust, many users don’t seem to understand it in depth. As we have been blogging on assertions – one needs to be very “pedantic”, i.e. detail oriented to be able to appreciate it, demonstrate it and understand it. We at TeamCVC have been pioneering assertions as a focus area since our PSL book days (end of 2003, http://www.systemverilog.us/psl_info.html ) and it has been almost a decade by now! We cover this in all our training sessions on assertions such as: SVA: http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf PSL: http://www.cvcblr.com/trng_profiles/CVC_LG_PSL_profile.pdf Even during our popular VSV course ( http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf ) we touch upon this topic during the program block discussion. Below is an extract from our training/book on SVA ( http://www.systemverilog.us/sva_info.html ): ...

Last week, our good friend Gaurav Jalan wrote a nice blog at: http://whatisverification.blogspot.in/2012/08/laws-and-verification.html   He has adapted Murphy’s law into Verification as: Applying to Verification ( http://whatisverification.blogspot.in/2012/08/laws-and-verification.html ) Moore’s law – Amount of code to be verified doubles every 2 years. Murphy’s law – Any code that isn’t verified will not work. Now as I recap on last week’s Verilog session delivered to an excited IIT-KGP audience, I realized the same law is applicable to slides/PPT/training too :-) Especially be careful with any code snippet shown in the slides – they  could be wrong – unless verified otherwise ! Now back to the title of this blog entry – what are the differences bet’n Verilog’s $display, $monitor & $strobe ? 1. Usual answer: $monitor is “continuous monitoring” – Yes, good For many fresh graduates the detail stops there – but not for those “verilog hungry, pedanti...