CVCBLR's VoW blog - Verification on the Web!

  As we wrap up an excellent UVM training for a well informed audience for a local customer at the very beginning of 2013, here is a quick tip for those verification work-horses trying to debug various UVM phase related hangs in their simulations. To be honest, this was developed for another customer way back in the middle of 2012, but never got published, so we decided to do it in early 2013. This is part of our product line where-in we line up various solutions around UVM. The scenario that several customers face is that they have bunch of raise & drop objections, but somehow there is a mismatch of the “raise-to-drop” – i.e. some of the raised objections remained and never got dropped! While UVM comes with few handy plusargs - +UVM_PHASE_TRACE, +UVM_OBJECTION_TRACE etc. these don’t always point you to exact problem, atleast fast-enough. Here is a smarter approach: The uvm_objection base class provides a very nice debug routine named display_objections() . One may want to...

If you are a verification engineer in ASIC/FPGA domain, chances are very little that you have not heard of SystemVerilog. For the last 6+ years it has been making positive impacts to design and verification teams across digital design space. Given this fact, this is no surprise there are several young engineers who jumped on to the bandwagon and picked up the language to a certain level. Many successful engineers in this part of the world have taken CVC ’s VSV course as a wise step towards the same. However when it comes to the production use, plain System Verilog falls behind in certain key areas. Make no mistake, it is a powerful language and is becoming even more powerful with the upcoming 2012 update. See our blog for more on those updates: www.cvcblr.com/blog Many users ask us – why do I need UVM on top of SystemVerilog. While there are ample number of marketing material available on the net for free on this, here is a humble, technical attempt to challenge a solid DV engi...

As some of our customers ask during our advanced SystemVerilog/UVM training sessions, SystemVerilog doesn’t allow multiple-inheritance. Or to be precise “DID NOT have”, now in SV-2012/2013 it does! For those yet to get there – here is  a quick recap:     Simple inheritance                  Few derived classes             One can of-course “derive” from another “derived class” too, as-in:   This is used widely in good System Verilog code and in general any OOP code. UVM uses this a lot as many of you who have been fortunate to have attended our popular UVM training sessions ( http://www.cvcblr.com/trainings ) across the world (Yes, we have delivered across India, various cities, across the globe as in Europe, Asia etc.). However what was not allowed in older SystemVerilog (2005/2009) is: Multiple inheritance, as in:...

Ever played with SystemVerilog DPI (Direct Programming Interface)? Most of the verification engineers coming from EC/EE background, they have hard time debugging C code in general. Things get complicated when you deal with multi-logic-valued system such as Verilog/SV (0,1,Z,X) and 2-state system such as C. See the standard data type matching slide we deliver during our popular VSV training : ( http://www.cvcblr.com/trainings ):   In case you can memorize the table above and use it each and every time when you touch DPI – perhaps you maynot need this post much. But for the 99.9% users who don’t or don’t want to do that, tools like Questa provide you a very handy option called -dpiheader Let’s see it in action: Consider a simple DPI import declaration as below:   Corresponding C-code looks like: So far so good? For those who have “spotted” the bug, pat yourself and continue reading. Others – any issue so far? Let’s see what the simulation output from Ques...

A well known aspect of constraint solving is the ability to classify hard vs. soft constraints. A quick Google search on “soft constraints” would lead you to; http://www.constraintsolving.com/tutorials/soft-constraints-tutorial in case you are interested in theory. Taking a practical example, given the holiday season around the corner many of us would like to travel, book tickets etc. Let’s say that we want to travel from City-1 to City-2 (Say Bangalore to Chennai); the source & destination are fixed and are non-negotiable. But how we travel can be based on preference/availability/cost etc. For instance one may have options of: Flight Bus Train Car Now modeling the above scenario using a constraint specification language like the one in SystemVerilog, there are “constraints” as below; class my_travel_c;   rand places_t src, dst;   rand int cost;   rand travel_mode_t travel_mode;   // Non-negotiable src and dest locati...

If you are involved in functional verification I am sure you have atleast heard of System Verilog as the IEEE standard. The first IEEE standard was released back in 2005 and went in for a revision during 2009. Now there is yet another major update – 2012, expected to be fully ratified by early 2013 (on time for DVCon 2013). Here is a nice blog on this: http://blogs.mentor.com/verificationhorizons/blog/tag/ben-cohen/ A major part of this new version is all about assertions/SVA. If you need a detailed list of changes and examples, with applications – look no further, get hold of our new SVA 3rd edition @ SVA book 3rd edition @Amazon In this article I wanted to introduce another nice, tiny, handy feature – unique constraint in SV. To give a background, consider a classical crossbar switch:   While every CPU can talk to/access every memory, for every access uniqueness must be maintained in terms of one-to-one connection. This is usually referred to as “Uniqueness Constraint...

  UVM Runtime Phasing and Phase Jumping Survey If you are well aware of UVM runtime phasing/phase jumping issues, quickly help yourself and the UVM community at large by filling out this survey: Verilab UVM Phasing Survey Now for a background and for those who are “undecided” whether or not I have an issue with it, here is more information: One of the significant updates done to OVM while bringing up UVM as the standard for verification methodology was the phasing. (For a detailed paper on user issues with OVM phasing approach, see: http://www.synopsys.com/community/snug/india/pages/abstracts.aspx?loc=india&locy=2011 and https://www.synopsys.com/news/pubs/snug/india2011/TA1.2_Intel_paper.pdf ) As with any standard development, there are differing view points coming from various experts, users etc. around the globe.India being the most vibrant Verification geography, it is very probable that many of the verification leads here face these problems day-in and day...